Dears：
The product uses NXP TEF8102 program 5 pieces of cascade, after FPGA processing, the data is transferred to NXP S32R294 for transmission. Currently, when debugging TEF8102 cascade, it is found that the trigger pin control cannot be used. The specific information is as follows:
Below are instructions for configuring the trigger pin：
The register description is detailed below：
bit 1 display is not USED. How should I configure this register? Thanks!
