T2080 processor and ddr3 memory adress mirroring

[Sassad]

Hi Experts,

I am doing layout of T2080 processor and 10GB DDR3 MEMORY chips ( total 10 chips). 

The memories are dual rank with shared address bus. 

My question is can we use address mirroring to resduce the layout complexity and better SI while designing T2080 and ddr3 memory chips interface? 

This is an urgent query. Your promt support will be extremely valueable. 

[Sassad]

Thanks for reply. Now i understated that I can mirror address and data signals too. 

Please also confirm if we can also mirror command and control signal too in dual rank memory . Can you please also specify if there is any signal that we cannot mirror or swap? 

[yipingwang]

according to T2080 reference manual,
there is only address mirroring for certain address bus, no other command and control signals for mirroring.

When bit DDR_SDRAM_CFG_2[MD_EN] = 1 is set, the controller will know to swap these signal before transmitting to the DRAM.
The controller will assume that CS0 is original bank and CS1 is the 'mirrored' rank of memory.
The following signals are mirrored:
MBA[0] vs. MBA[1];
MA[3] vs. MA[4];
MA[5] vs. MA[6];
MA[7] vs. MA[8]).
no other signal for mirroring.

[Sassad]

Thanks. It is clear now for address bits mirror.

Can you plz confirm regarding data bus too. Can we randomly swap the data bits within each byte lane or there are specific data bits too like address bits? 

Your support jas been really helpful so far. 

[yipingwang]

T2080 DDR3 doesn't support DQ_mapping.

In the T2080 Reference Manual, there is no mention of any registers similar to DQ_MAP or configurable DQ mapping.

This means that the DQ signals must be connected in a fixed sequence, that is:

The DQ0 of the DDR controller must be connected to the DQ0 of the DRAM, DQ1 corresponds to DQ1, and so on.

[Sassad]

Last quick question

We have address bus of A0 to A14.

Can we swap as you said in following order

A0 to A1

A2 to A3

A4 to A5

A6 to A7

A8 to A9

A10 to A11

A12 to A13

A14 to A0

Is this the correct order of swapping? Please confirm. 

[yipingwang]

No, these are not  the correct order.

These pins cannot be connected randomly.

The controller will assume that CS0 is original bank and CS1 is the 'mirrored' rank of memory.

Only the following signals are mirrored for DDR3 on T2080:

MBA[0] vs. MBA[1];

MA[3] vs. MA[4];

MA[5] vs. MA[6];

MA[7] vs. MA[8]).

no other signal for mirroring, user can refer to DDR_SDRAM_CFG_2[MD_EN] in T2080 Reference Manual.

[yipingwang]

yes, you can use address mirroring to reduce complexity and improve signal integrity, especially when dealing with dual-rank memory configurations.

In dual-rank design, address mirroring means that the second rank has certain address and control signals intentionally swapped (mirrored),
this is done to:
- reduce simultaneous switching noise
- improve signal integrity
- simplify PCB routing

Layout tips:
- route address/control signals to both ranks with minimal vias.
- use fly-by topology for DDR3 (recommended for high-speed).

DDR driver sets DDR_SDRAM_CFG_2[MD_EN] = 1 when address mirroring is used.