SPT3.1 1024-128-16range don't work!

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SPT3.1 1024-128-16range don't work!

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Shi_test
Contributor III

S32R45:

The s32ds project is "RSDK_offline_example".

SPT:"range_1024smp_128crp_16ch.pspt"

I try "./xxx.elf" in S32R45 linux,but It seems to be stuck with "pdma" command in "range_1024smp_128crp_16ch.pspt".

This pic have pdma.

Shi_test_0-1679479371167.png

This pic not have pdma.

Shi_test_1-1679479408800.png

  • Has anyone tested it successfully?

 

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Shi_test
Contributor III

I solved the problem.

The reason is I need to match S32DS input with SPT input.

在原帖中查看解决方案

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Shi_test
Contributor III

I solved the problem.

The reason is I need to match S32DS input with SPT input.

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petervlna
NXP TechSupport
NXP TechSupport

Hello,

So little information has been disclosed for analysis:

  1. What RSDK version are you using?
  2. What hardware are you using? If are you using RSDK pre-build demo, I can confirm it works well on the S32R45 EVB. Based on the snapshots you provided, I don't think the PDMA instruction will the stuck program, if there is an error with PDMA, the program won't stop there and will throw out an error message via an interrupt.

Best regards,

Peter

 

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Shi_test
Contributor III

I tried to confirm that something was wrong with PDMA:

pdma.ind .signext .16cmplx .opram2sysram .sync .notrace .nocoherent, CHANNELS_NO*OUTPUT_SAMPLES_PER_CH, RSDK_SPT_CUBE_BASE_ADDR, WR_16, 0x0, 0x1, (8*(CHIRPS_PER_FRAME - 1)), 0x8

Shi_test_0-1679651224906.png

If PDMA is not stuck,terminal will have "times:1",but there is "0".

 

Shi_test_1-1679651848186.png

If i change ".sync" to "async",terminal will have "times 1".So i'm sure PDMA is not stuck.

 

And then i change "WR_16" to "WR_11",PDMA will go on.

So i check "WR_16":

add .noshift .mod24 WR_5, #(OR_2_0_0), WR_16

use the same method I find that "WR_5" is the source

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Shi_test
Contributor III
1.SDK:Rev.1. 1 .0 S32DS:3.4 and 3.5
2.S32R45 Evaluation Board
Yes, From the phenomenon, the error is WR_5.In 16 channels SPT,WR_5 is Work Registers for OUTPUT buffer.
So,Could WR_5 possibly lead to this outcome?(may be WR_5_CTRL_REG)
I will try SDK1.0.0.
Thank you.
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Shi_test
Contributor III
SDK1.0.0 is no better than SDK1.1.0.
I can't find the reason.
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Shi_test
Contributor III

Shi_test_0-1679642030175.png

  • And then we analyze it again and we get WR_5,if we change WR_5,it will succeed,but the result still wrong. 

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Shi_test
Contributor III

I already know which parameter is the problem.

There is PDMA command:

pdma.ind .signext .16cmplx .opram2sysram .async .notrace .nocoherent, CHANNELS_NO*OUTPUT_SAMPLES_PER_CH, RSDK_SPT_CUBE_BASE_ADDR, WR_16, 0x0, 0x1, (8*(CHIRPS_PER_FRAME - 1)), 0x8

If I replace WE_16 with WR_20.He's going to succeed.

But i still don't know why.

There is Reference Manual pic about WR_16-31:

Shi_test_0-1679636205841.png

 

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petervlna
NXP TechSupport
NXP TechSupport

Hello,

I have contacted RADAR team. They will post here ASAP.

Best regards,
Peter