SJA1000 bus errors

[iankey]

I am using the SJA1000T in a circuit, with a PIC processor and TI transceiver. I have put it into local self test mode, writing 0x10 into CDR when the buffer is loaded. I get an initial transmission, but with a start frame error.

Is there anything wrong with the circuit?

I have tried different configurations of the output FETs (OCP0, OCN0 and OCPOL0) with no effect and no transmission.

Initialisation:

Intel mode,

reset mode,

CDR = CLKOUT=off, PeliCAN mode, bypass comparator

OCR = various different options

speed = 1Mbps (16MHz sys clock, btr0=0x00, btr1=0x14)

set all AMR to 0xff (disabled, I believe)

IER = 0xff (enable all interrupts) -> don't see any on the processor

set mode to local-self test (bit 2 set)

For transmission:

write the ID, write INFO and then data

Set bit 4 in CMR

Am I doing anything wrong?

[martin_kovar]

Hello Ian,

I received answer from my colleague:

There is no problem in the device.

Does customer use AN97067 App note?

I don’t see Acceptance code register set, cleared? Is that done?

CMR bit 4 is go to sleep?

 

Timings can also be wrong...

Best Regards,

Martin

[iankey]

Thanks for the information. Yes, I am using the app note AN97076 as well as the data sheet. I didn't realise there was a contention in the data. Following section 5.7 of the app note, is states "Self Reception Request is CMR=0x10". In fact, I have datasheet 2000 Jan 04 and it states on page 23, CMR.4 = SRR (Self Reception Request". When was this bit altered and where can I find the 'correct' datasheet?  If CMR.4 is now go to sleep, how do loopback/self-tests get performed?

Thanks
Ian

(PS. Apologies for the delay in responding, I was out of the country for a week

[martin_kovar]

Hello Ian,

I contacted my colleague and I am waiting for his answer. I will write you back as soon as I get any feedback.

Regards,

Martin