SGLT5000 Capless Headphone Mode

[mohamedhusain13]

Hi,

When playing audio through the SGTL5000 audio codec, we seeing a 1.6V DC bias voltage in the Right and Left headphone lines.

We enabled the capless headphone mode using CAPLESS_HEADPHONE_POWERUP bit in CHIP_ANA_POWER Register. But still we are seeing a 1.6V in the signals.

Our understanding is that with the capless headphone mode, a charge pump is used to swing the audio signals in positive and negative voltage range, thus removing the need for DC Bias.

Please let us know if there any way to reduce this DC Bias value to zero.

Note : We are seeing the 1.6V only after enabling the VAG_POWERUP bit.

Thanks in advance,

Mohamed Husain

[JozefKozon]

Hi Mohamed Husain,

are you seeing the 1.6DC bias voltage against the HP_VGND virtual ground or against the AGND/GND? Could you please provide your schematic and code? Please also provide the details below.

Customer: ?

End Customer: ?

End Application: ?

Country: ?

Annual Volume: ?

With Best Regards,

Jozef

[mohamedhusain13]

Hi Jozef,

Observation on HP_R and HP_L:
* HP_R & HP_L against to Virtual ground - Voltage obtained is 1.6V when headphone is not connected (but audio signal is provided to audio jack in this case through codec)
* HP_R & HP_L against to Virtual ground - Voltage obtained is 1.2V when the headphone is connected and audio signal is enabled to headphone through codec.

Please find the attached schematics for Audio section (audio codec and Headphone). - SGTL5000 - Audio codec and Headphone.png

The actual issue we are facing is with HP_DETECT signal. HP_DETECT signal (refer the attached schematics part) will be used to detect the insertion and removal of headphone jack. As you can see in the schematics, the HP_DETECT signal will be connected to the HP_R (right side headphone out) in the audio jack during the headphone jack is not inserted. Due to the DC bias, we are seeing 1.6V in the HP_DETECT even when the headphone is removed (in this case, actually the HP_DETECT signal is supposed to be in 0V). Please let us know any steps to reduce the DC bias voltage so that we can detect the removal of Headphones or let us know if there are any other ways to detect the headphone removal.

Also if the audio codec can automatically detect the headphone connection, please let us know if we can identify the same through some registers.

Kindly note the below requested details.

Customer: e-consystems
End Customer: Cannot be disclosed due to NDA
End Application: Media device
Country: India
Annual Volume: 1k/year.

[JozefKozon]

Hi Mohamed Husain,

I have contacted an application engineer with your question. He needs a schematic with a better resolution. Could you please provide? The schematic you posted is blurred and hard to read. 

With Best Regards,

Jozef

[mohamedhusain13]

Hi Jozef

Please find the pdf file of the diagram - Audio_section.pdf

Thanks,

Mohamed Husain

[JozefKozon]

Hi Mohamed,

please see a reply from the application engineer.

DESCRIPTION

In customer schematic, both VDDA_CODEC and VDDIO_CODEC are supplied from VCC_3P3_BB. If the VDDA and VDDIO either is above 3V, 0.1uF capacitor on the CPFILT(pin18) must not be placed.

Is the capacitor(C149) placed on the customer board? If yes, please remove it.

With Best Regards,

Jozef

[mohamedhusain13]

Spoiler

Hi Jozef,

Thanks for your reply.
We did not connect the 0.1uF capacitor on the CPFILT (pin18) pin. Please let us know if any other things need to consider for detect HP removal.

Thanks,
Mohamed Husain

[JozefKozon]

Hi Mohamed,

is there any change in the HP bias voltage after the removal of the 100nF capacitor?

With Best Regards,

Jozef

[mohamedhusain13]

There are no changes in the bias voltage after the removal of 100nF capacitor as well. Please let us know what can be done further

[JozefKozon]

Hi Mohamed,

I have just received an answer from the application engineer. He has couple of suggestions. Please follow it and please provide the results. Please see below and a schematic attached.

DESCRIPTION

For customer schematic, there are some differences on the HP capless output design between SGTL5000 EVK and customer schematic.

1. In customer schematic, there are two GND  net and three ESD suppressors are connected HP L/R to other GND. How does customer probe HP output signal? When measuring the signal, which GND network the probe detect?

2. Why does customer add common filter(L10) in HP L/R output?  Could they remove it and test again? The attachment is SGTL5000 EVK schematic. There is capless design in the schematic. Customer can refer to it.

With Best Regards,

Jozef

[Jab_1]

Hi Jozef

Sorry for the late reply
This is Jabir from Mohamed's team,
Please find our reply in inline

"1. In customer schematic, there are two GND net and three ESD suppressors are connected HP L/R to other GND.
How does customer probe HP output signal? When measuring the signal, which GND network the probe detect?"

We probed the HP output signals with respect to the normal GND while playing the audio signal from audio codec.

"2. Why does customer add common filter(L10) in HP L/R output? Could they remove it and test again? The attachment is SGTL5000 EVK schematic.
There is capless design in the schematic. Customer can refer to it."

We removed the common mode filter and performed the test and observed 1.6V still there in HP output lines.

Please let us know is any other things to consider for HP detection.

Thanks,
Jabir

[JozefKozon]

Hi Jabir,

the application engineer requests test waveforms. Could you please provide? Please see below.

DESCRIPTION

Could customer share the HP out test waveform? Thanks.

With Best Regards,

Jozef