SC18IS606 clock stretching?

[Winter1]

Hello NXP-Team,

we used the SC18IS602B, which is now end of life, without problems and have now switched to the successor SC18IS606, with whom we now have I2C communication problems.

In the attachment is a picture of a failed I2C transmission. The address pins of the SC18IS606 are connected to GND, therefore the address is 0x50. In the picture you can see the address bytes of the message, for wich our microcontroller does not recognize the acknowledge.

For me it looks like the SC18IS606 takes over the bus (both for CLK and Data) after the falling edge of the 8 clock. The low level voltage is lower than before and the rising edge of the 9 clock is delayed to 12µs. The SC18IS606 puts the Acknowledge on the bus shortly before the rising edge of the 9 clock.

The Problem is, that our microcontroller is reading a Not Acknowledge for this transmission. The microcontroller does not support clock stretching, so he reads the Data bus 10µs after the 8 clock. At this time the Acknowledge is High.

Can you confirm that the SC18IS606 is stretching the clock for the Acknowledge?

Thanks in advance.

[Summer1]

Hello Thomas and Winter1,

are there any new informations regarding the topic?
We run into the same problem.

The two oszilloscope screenshots in the attachment show the diffrence between the acknowledge of the 602 and 606.

Thanks in advance!
Summer1

[Winter1]

Our microcontroller does not support clock stretching, which the SC18IS606 apparently does. Our solution was to slow down clock.

[Summer1]

Thanks for the reply, we will try to slow down the clock as well and hope this will not cause further timing issues.

We use galvanic isolation in the I2C signal chain with a unidirectional SCL channel. Therefore our system does not support clock stretching either.

[TomasVaverka]

Hello Andrej,

I have not heard about such an issue yet.

Regarding your question, I think the answer is in the datasheet:

BR, Tomas

[Winter1]

Hello Tomas,

thanks for your fast answer. Yes the datasheet says, that the SC18IS606 can stretch the clock. It just sounds odd to me, that the SC18IS606 needs to stretch the clock due to internal processing, when it recives its address. My concern is that we have another problem and I wanted a confirmation that the chip is already stretching the clock after receiving his address.

[TomasVaverka]

Hello Andrej,

The device does have the ability to do clock stretching, but normally at the first address write the device should not do clock stretching because the device would not be busy at this time. The write to 0x50 address should be as shown below.

After the device is powered up, can your I2C master wait for a second or so to allow the device to completely initialize before the I2C master starting to write to the device? Does this fix this issue?

BR, Tomas

[Winter1]

Hello Tomas,

thanks for your efforts!

On your picture you can see exactly what I mean. The bus frequency is 400kHz (2,5µs). After the falling edge of the 8 clock the master releases the bus and SDA goes high (not acknowledge). Unfortunately we can not see the 9 clock on SCL, but it is obvious, that it does need much more time than 2,5µs (clock stretch?).

Greetings Winter