SAF85XX L2 Cache Invalidation and Flush

[eddy_bts]

Cortex A53 core which is located in SAF85XX has two types of caches. L1 and L2.

Zephyr cache-related code is like:

#include <cache.h>

#include <syscall_handler.h>

static inline int z_vrfy_sys_cache_data_all(int op)

{

    return z_impl_sys_cache_data_all(op);

}

#include <syscalls/sys_cache_data_all_mrsh.c>

static inline int z_vrfy_sys_cache_data_range(void *addr, size_t size, int op)

{

    Z_OOPS(Z_SYSCALL_MEMORY_WRITE(addr, size));

    return z_impl_sys_cache_data_range(addr, size, op);

}

#include <syscalls/sys_cache_data_range_mrsh.c>

static inline int z_vrfy_sys_cache_instr_all(int op)

{

    return z_impl_sys_cache_instr_all(op);

}

#include <syscalls/sys_cache_instr_all_mrsh.c>

static inline int z_vrfy_sys_cache_instr_range(void *addr, size_t size, int op)

{

    Z_OOPS(Z_SYSCALL_MEMORY_WRITE(addr, size));

    return z_impl_sys_cache_instr_range(addr, size, op);

}

#include <syscalls/sys_cache_instr_range_mrsh.c>

APIs above is applied to L1 and L2 cache both? Otherwise only to L1 cache?

Please let me know how to flush or invalidate L2 cache.

[petervlna]

Hello,

The [Zephyr Cache Management API](https://docs.zephyrproject.org/3.3.0/hardware/cache/index.html) is a generic API for any type of I/D caches, either implemented by the architecture, for instance, in case of L1/L2 caches available in the core itself like Cortex-A53; or implemented by a cache controller driver, for instance, in case of L2 caches externals to the core. This API can be enabled in your driver/application through [CONFIG_CACHE_MANAGEMENT](https://docs.zephyrproject.org/latest/kconfig.html#CONFIG_CACHE_MANAGEMENT)
The code you are looking for the cache management on A53, is in zephyr/arch/arm64/core/cache.c for v2.7.2 (latest SAF85xx release).
The only APIs implemented are for D-cache and operate over all the cache levels implemented in the core. When acting over all cached memory, it does it by set/way. When acting over a range of memory (VA), it does it to PoC (point of coherence, which is always outside the processor).

There’s also a chapter available in Auto Zephyr user manual, “8.2.1 Non-Cacheable section on core A53” from SW32SAF85xx_AZ_2.7.2_0.9.0_D2208__User_Manual.pdf
Zephyr allows to create a “nocache” read-write memory section configured as no-cache through [CONFIG_NOCACHE_MEMORY.](https://docs.zephyrproject.org/latest/kconfig.html#CONFIG_NOCACHE_MEMORY)

Best regards,

Peter

[petervlna]

Hello,

The issue is currently being analyzed. Could you tell me which specific file the code in question comes from?

Best regards,

Peter

[eddy_bts]

zephyr/arch/arc/core/cache.c

[petervlna]

Hello,

I have created internal ticket for this. The RADAR team will either reply here, or I will share answer.

Best regards,

Peter