S32R41: How to Enable and Verify Cortex-M7 Lockstep Functionality

[wangkaixiang]

Hello NXP Team,

I am working with the NXP S32R41 automotive radar SoC and using Lauterbach TRACE32 for debugging.

I would like to understand how to enable and verify the hardware lockstep functionality of the Cortex-M7 cores on the S32R41.

Could you please help clarify the following questions?

1. How to enable Lockstep: Is the Cortex-M7 lockstep mode enabled by default on the S32R41, or does it need to be configured? If configuration is required, what are the exact steps to enable it? Is it controlled by hardware configuration, DCF records, startup software, or specific registers?

2. Configuration registers: Which S32R41-specific registers and bit fields indicate whether Lockstep is enabled? Please provide the register names, addresses, bit positions, and expected values.

3. How to verify Lockstep: How can I confirm that the Cortex-M7 cores are actually operating in hardware lockstep mode rather than independent mode? Is checking the configuration register sufficient, or are additional status registers required?

4. Lockstep error detection: Which registers indicate the status of the lockstep comparator? How can I determine whether the comparator is functioning correctly and whether any lockstep mismatch has been detected?

5. TRACE32 debugging: Is there a recommended TRACE32 command sequence or debugging procedure to inspect the lockstep configuration and status?

6. Documentation: Could you point me to the relevant sections of the S32R41 Reference Manual, Safety Manual, or other official documentation describing the lockstep configuration and verification procedure?

I want to ensure that the lockstep functionality is correctly enabled and that its operation can be verified using documented, S32R41-specific methods.

Please note that I am specifically asking about the S32R41, not the S32K3 family, so I would appreciate register definitions and procedures applicable to the S32R41.

Thank you for your support.

Best regards

[petervlna]

Hello,

On the S32R41, the Cortex‑M7 processors are implemented as hardware lockstep core pairs. Lockstep operation is part of the S32R41 hardware configuration and is not enabled by application software, startup code, or an S32K3-style UTEST_MISC[LOCKSTEP_EN] DCF record. The NXP S32R41 product information explicitly describes the Cortex‑M7 implementation as having a lockstep core configuration.

1. No software enable sequence is required

2. The configuration should not be verified using S32K3 registers

3. Debugger visibility provides a practical architectural indication

• TRACE32 connects to the logical Cortex‑M7 processor. It does not present the redundant checker core as an additional independently debuggable Cortex‑M7. Therefore, only the functional member of each lockstep pair is expected to appear as a debug target.

4. Lockstep mismatch reporting

• A mismatch detected by the Cortex‑M7 lockstep comparison logic is reported through the S32R41 safety fault-management path. The application must configure the corresponding FCCU fault and its required reaction in accordance with the S32R41 Safety Manual.

5. No special TRACE32 command is required to enable lockstep.

6. Please refer to the following S32R41-specific documents:

• S32R41 Reference Manual, particularly the Cortex‑M7, FCCU and reset/fault-management chapters;
  S32R41 Safety Manual, particularly the safety mechanisms covering Cortex‑M7 lockstep execution, lockstep comparison and FCCU fault handling;
  the device-specific FCCU fault mapping associated with the applicable S32R41 revision;
  the TRACE32 S32R41 startup scripts supplied with the supported S32R41 software/debug package.

Best regards,

Peter