PTN3460I flickers and switches off display brightness

[sergeyvelykokha]

Hi all,

We are using PTN3460I and in new mainboard we got following effect in some boards: in several minutes after it switched on it starts to flicker and in several seconds display goes black. As I see the BLKTEN goes low. Since we are using Linux4.19 the activated KMS debugging shows that HPD generates IRQ and link training failed (s. messages bellow)

With oscilloscope I see realy two low pulses on HPD with nearly 0,7mS duration.

But could not find any reference in datasheet why the HPDRX pin of PTN3460I goes low during normal operation. Why it did so? Is it possible to get any further information from chip why it generated IRQ on HPD and what goes wrong in training phase?

Thanks an lot,

Happy new 2020

Sergey

[  115.092696] got hpd irq on port A - short
[  115.094502] DPDDC-A: 0x00000 AUX -> (ret= 15) 11 0a 82 01 00 03 01 81 00 01 00 00 0f 00 00
[  115.096919] DPCD: 11 0a 82 01 00 03 01 81 00 01 00 00 0f 00 00
[  115.098859] DPDDC-A: 0x00100 AUX <- (ret=  2) 0a 82
[  115.099727] DPDDC-A: 0x00200 AUX -> (ret=  1) 01
[  115.101554] DPDDC-A: 0x00107 AUX <- (ret=  2) 00 01
[  115.102245] DPDDC-A: 0x00080 AUX -> (ret= 16) 09 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[  115.103222] Using vswing level 0
[  115.106305] Using pre-emphasis level 0
[  115.106840] DPDDC-A: 0x00201 AUX -> (ret=  1) 00
[  115.107441] Using DP training pattern TPS1
[  115.109184] DPDDC-A: 0x00202 AUX -> (ret=  6) 00 00 80 00 00 00
[  115.111512] DPDDC-A: 0x00102 AUX <- (ret=  3) 21 00 00
[  115.113559] DPDDC-A: 0x00202 AUX -> (ret=  6) 11 00 80 00 00 00
[  115.115252] clock recovery OK
[  115.116111] Using DP training pattern TPS2
[  115.117544] DPDDC-A: 0x00102 AUX <- (ret=  3) 22 00 00
[  115.119962] DPDDC-A: 0x00202 AUX -> (ret=  6) 71 00 80 00 11 00
[  115.121649] Using vswing level 1
[  115.122563] Using pre-emphasis level 0
[  115.123871] DPDDC-A: 0x00103 AUX <- (ret=  2) 01 01
[  115.126118] DPDDC-A: 0x00202 AUX -> (ret=  6) 71 00 80 00 22 00
[  115.127803] Using vswing level 2
[  115.128715] Using pre-emphasis level 0
[  115.130019] DPDDC-A: 0x00103 AUX <- (ret=  2) 02 02
[  115.132275] DPDDC-A: 0x00202 AUX -> (ret=  6) 71 00 80 00 33 00
[  115.133957] Using vswing level 3
[  115.134894] Using pre-emphasis level 0
[  115.136201] DPDDC-A: 0x00103 AUX <- (ret=  2) 27 27
[  115.138451] DPDDC-A: 0x00202 AUX -> (ret=  6) 71 00 00 00 33 00
[  115.140138] Using vswing level 3
[  115.141050] Using pre-emphasis level 0
[  115.142375] DPDDC-A: 0x00103 AUX <- (ret=  2) 27 27
[  115.144712] DPDDC-A: 0x00202 AUX -> (ret=  6) 71 00 00 00 33 00
[  115.146400] Using vswing level 3
[  115.147310] Using pre-emphasis level 0
[  115.148612] DPDDC-A: 0x00103 AUX <- (ret=  2) 27 27
[  115.149990] ln0_1:0x71 ln2_3:0x0 align:0x0 sink:0x0 adj_req0_1:0x33 adj_req2_3:0x0
[  115.149991] Channel equalization failed 5 times
[  115.153412] [CONNECTOR:81:eDP-1] Link Training failed at link rate = 270000, lane count = 2
[  115.153429] [CONNECTOR:81:eDP-1]
[  115.156729] DPDDC-A: 0x00102 AUX <- (ret=  1) 00
[  115.168003] DPDDC-A: 0x03000 AUX -> (ret=  1) 00
[  115.169720] DPDDC-A: 0x00201 AUX -> (ret=  1) 00
[  115.171540] DPDDC-A: 0x00202 AUX -> (ret=  6) 71 00 00 00 33 00
[  115.173269] running encoder hotplug functions
[  115.174818] Connector eDP-1 (pin 4) received hotplug event.
[  115.176476] [CONNECTOR:81:eDP-1]
[  115.178115] DPDDC-A: 0x00500 AUX -> (ret= 12) 00 60 37 33 34 36 30 49 00 11 01 00
[  115.180226] DP branch: OUI 00-60-37 dev-ID 3460I HW-rev 1.1 SW-rev 1.0 quirks 0x0000
[  115.183085] DPDDC-A: 0x00202 AUX -> (ret=  6) 71 00 00 00 33 00
[  115.185193] DPDDC-A: 0x03000 AUX -> (ret=  1) 00
[  115.186980] DPDDC-A: 0x00201 AUX -> (ret=  1) 00
[  115.188828] DPDDC-A: 0x00202 AUX -> (ret=  6) 71 00 00 00 33 00
[  118.199806] Turning eDP port A VDD off
[  118.200895] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
[  118.202826] disabling DC off
[  118.203796] Enabling DC5
[  118.204515] Setting DC state from 00 to 01

[sergeyvelykokha]

Hi Tomas,

Thank you for answer. It helps a lot.

But one more question to this one: described effect occurs in already third prototype (in previous DP-LVDS worked fine). Our HW developer checked layout and she means that there are no differences in routing of DP signals comparing to old prototypes. Also I see that in current boards the effect comes not directly at start, the boards (where it occurs) need several minutes. After warming up it is happening even in BIOS GUI. Is it possible that this effect occurs when the  central pad bad soldered?

Thank you,

Best Regards,

Sergey

[TomasVaverka]

Hi Sergey,

Did you observe this issue on many devices or only one device? Did you try to replace PTN3460I on faulty board by a new PTN3460I?

Yes, if the central pad is bad soldered, then it may be causing bad grounding and issues as well.

Best regards,

Tomas

[sergeyvelykokha]

Hi Tomas,

We got several boards where the center pad of PTN3460I was good soldered and we gets again the same effect. We are trying to find the reason. One of the ideas is to get the DP link running with reduced bit rate of 1,62Gb/s. Now just for test.

But unfortunately I'm pretty novice in this area. As I see the PTN3460I supports this RBR, but the Linux kernel at start decides to use the HBR of 2,7Gb/s:

[    0.409801] Modeline 0:"1280x800" 60 71099 1280 1344 1380 1440 800 810 813 823 0x40 0xa
[    0.410484] adjusted mode:
[    0.410722] Modeline 0:"1280x800" 60 71099 1280 1344 1380 1440 800 810 813 823 0x40 0xa
[    0.411424] crtc timings: 71099 1280 1344 1380 1440 800 810 813 823, type: 0x40 flags: 0xa
[    0.412116] port clock: 270000, pipe src size: 1280x800, pixel rate 71099
[    0.412697] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
[    0.413192] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[    0.413717] ips: 0, double wide: 0

My questions: how can I get the RBR? Could I activate it via any register setting in PTN3460I, or in any other way?

And one more question: is it possible (when yes, then how) to configure via registers for using of only one DP lane? I found that it is possible only via CFG3 pin

Thanks a lot for support,

Best Regard,

Sergey

[sergeyvelykokha]

Hi Tomas,

Thanks a lot for answer and for attached datasheet. My problem was that I had the datasheet for PTN3460 and the 0x80 register has other content:

Yes, my error...

But before of your last answer I found how to modificate the driver to use only one DP lane and to use RBR instead of HBR. Out tests show that with two lanes and RBR all works fine.

I am sure now that we have not only soldering of center pad but also the layout problems (as you wrote in yours first message here)

Thank you a lot for support,

Best Regards,

Sergey

[TomasVaverka · Accepted solution]

Hi Sergey,

Yes, please refer to the attached AN11606 to change configuration register 0x80[bit 3] = 1b (default setting is 0), so that DP sink (PTN3460I) will report to the DP source that it only supports RBR link rate. And then DP source will only use RBR link rate to start DP link training.

As for your second question, yes, and there are two ways to do it:

1. Hardware pin (CFG3 pin) strapping: Set CFG3 pin = HIGH, and PTN3460I will report to DP source that it only supports 1 lane DP.

2. Configuration register settings:

A. Set configuration register 0x8E[bit 2] = 1b, so that PTN3460I CFG3 pin setting will be overwritten by configuration register setting after power on.

B. Set configuration register 0x80[bit 2] = 1b, so that PTN3460I will report to DP source that it only supports 1 lane DP.

Best regards,

Tomas

[sergeyvelykokha]

Hi Tomas,

>Did you observe this issue on many devices or only one device?

In nearly 30% of prototypes. 

After I wrote my last question we got the X-Ray results from one board with this effect. For this board I can say that the center pad is not soldered. I guess with other boards where it ocures we have same problem. 

Thank you for support, I guess the reason found and if we get any other problems with it, I will write here

Best regards,

Sergey

[TomasVaverka]

Hi Sergey,

Please refer to the the DisplayPort specification for HPD behavior.

The 0.7 mS HPD pulse is called IRQ_HPD pulse which is for DP sink device (PTN3460I) to inform DP source device (PC) that DP link synchronization has been lost (see below from DisplayPort specification).

So “two low pulses on HPD” means the DP link training was failed and PTN3460I reported two time of DP link synchronization loss to source (PC).

According to the debug log “[  115.188828] DPDDC-A: 0x00202 AUX -> (ret=  6) 71 00 00 00 33 00”, DPCD register 0x202 = 0x71 which means DP link training was done successfully (DP register 0x202 bit [2-0] = 0x07) on lane 0, but failed on lane 1 (DP register 0x202 bit [6-4] = 0x01 which means lane 1 failed at training pattern 2), so you need to check the PCB layout difference between DP lane 0  and lane 1 to see why lane 0 can pass DP link training, but lane 1 cannot.

Hope it helps!

Best regards,

Tomas