Hi,
Correct, bus capacitance limit is specified to limit rise time reductions and allow operating at the rated frequency. There are several strategies available to cope with excess bus capacitance:
- Reduced fSCL: The bus may be operated at a lower speed.
- Higher drive outputs: Devices with higher drive current such as those rated for Fast-mode Plus can be used.
- Bus buffers: There are a number of bus buffer devices available that can divide the bus into segments so that each segment has a capacitance below the allowable limit, such as the PCA9517 bus buffer or the PCA9546A switch.
- Switched pull-up circuit: A switched pull-up circuit can be used to accelerate rising edges by switching a low value pull-up alternately in and out when needed.
I recommend you take a look at the section 7.2 of the I2C Bus Specification for more detailed information about how to calculate if the 10’s of kHz you are planning to use in your application is sufficient to avoid problems with the excess of capacitance on the bus. If this don’t work, I would recommend you to use a bus buffer to isolate the capacitance between bus segments.
I2C Bus Specification: https://www.nxp.com/docs/en/user-guide/UM10204.pdf
Regards,
Jose
