Greetings NXP Community,
I am in the process of configuring the MC33774A with the S32K311 using the SPI protocol. I would greatly appreciate if I could receive the SPI data frame details for both read and write operations, which should include Address, Data, and CRC for 64-bit comms.
Further, I would like to know what settings need to be configured in the MC33774A, in order to change mode from Deep Sleep to Active mode after it receives a Power-On Reset (POR).
SPI signal from the logic analyser is attached
Hello Karthik,
1. MC33774A SPI message format (64‑bit).
Clocking and edges (SPI):
- CPOL = 0 (SCLK idles low).
- Rising edge shifts the next bit out, falling edge is the sampling (valid) edge.
- The device decodes the frame on CSN rising edge (end of frame).
- A response to a read request is provided in the next SPI frame, send a NOP if you only need to clock out the pending response.
64‑bit frame field layout (MSB→LSB):
(Each “DATAx” is a 16‑bit word)
- CMD: 00=NOP/Wake, 01=Read, 10=Write, 11=Response
- MADD / CADD / DEVADD: Master/chain/device addressing fields retained from TPL format. In single‑device SPI use they are not used for bus arbitration, but they must be present in the header.
- MSGCNT: echoed in responses, otherwise ignored by device
- DATALEN: number of 16‑bit DATA words carried in this frame minus 1. For a 64‑bit transaction use DATALEN=0 → exactly one DATA word
- REGADD: 14‑bit start register address
- CRC[15:0]: frame CRC
Because the MC33774A returns read data in the next frame, you typically send (1) a read request, then (2) a NOP (CMD=00) to clock out the response (or another command if you want to pipeline).
64‑bit Write of a single 16‑bit register:
CMD = 10b (Write)
DATALEN = 00b (exactly one DATA word in a 64‑bit frame)
REGADD = target register (14‑bit)
DATA0 = 16‑bit value to write
CRC = per polynomial below
64‑bit Read of a single 16‑bit register
CMD = 01b (Read)
RESPLEN/NUMREG/PAD exist only in the read request format of the protocol to support multi‑read and padding. For a single 16‑bit register with a 64‑bit response, set RESPLEN=0 (1 register per response), NUMREG=0 (1 register total), PAD=0. (Even though these fields were introduced for TPL, the read‑request header structure is the same over SPI.) The device returns one 64‑bit response frame in the next SPI transaction.
CRC (for all frame lengths)
- Width: 16 bits
- Polynomial (MSB‑first): 0x3D65
- Seed: 0x0000
- Encode: compute over the whole frame from MSB down to bit 16 (CRC field is zero while computing), then append the 16‑bit CRC.
- Check: compute over the entire received frame including CRC; result must be 0x0000.
The datasheet provides CRC examples and expected results.
2. Exiting Deep‑Sleep after POR → Active
What happens on reset and what you must do:
- After POR, the device defaults to Deep‑Sleep.
- In Deep‑Sleep, only bus activity can wake the device, other wake sources are disabled. Upon detecting bus activity, the device transitions to Active. All other registers are reset, except the two deep‑sleep storage registers. The POR cause can be read from FEH_POR_REASON register.
- Timing: Deep‑Sleep → Active startup is up to 2.1 ms. The maximum wake‑up‑to‑communication time is 2.4 ms.
SPI wake & first commands (recommended sequence):
- From the S32K311 LPSPI, assert CSN low and transmit any valid SPI frame (e.g. a 64‑bit NOP or a benign read like SYS_VERSION @ 0x0010). This bus activity wakes the MC33774A from Deep‑Sleep. The first frame may not be processed, as it is used to wake the device.
- Wait ≥ 2.4 ms (Twake(com) max), then send the actual command (e.g. read SYS_VERSION (0x0010) and/or FEH_POR_REASON (0x0480) to confirm POR reason).
- You are now in Active mode. If you plan to enter Sleep/Cyclic later, you control the mode via SYS_MODE.TARGETMODE.
Notes & good practice:
- The datasheet explicitly states “device remains in Deep‑Sleep until it detects bus activity”; so no special “wake command” is needed on SPI beyond driving a frame. (A dedicated “wake frame” exists for TPL, not required for SPI.)
- On entering Active, a BIST runs and measurement results are invalidated until new conversions complete. If you read measurements immediately, check validity (8000h means invalid).
BRs, Tomas
Hi Thank you for your response,
I have made the spi frame and set up the spi, but AFE isn't reacting to the signal. can you please check that my configuration is correct or if something is wrong?
Thank you
