Loop back connection between High speed CAN transceiver and Low speed CAN transceiver at physical layer

[abhishekks]

We are using 2x (high Speed CAN) and TJA1055T/3/1J(Low Speed CAN) in our design.

We are going a head with production. 

We have looped HS_CAN1, HS_CAN2 and LS_CAN at physical layer. as shown in attachment. 

Please let us know whether looping HS_CAN to LS_CAN is fine? 

If not please suggest if you have any method to test Low speed CAN.

Regards,

Abhishek 

[lukaszadrapa]

Hi,

this is not recommended, physical layer of high speed CAN and fault tolerant CAN is not compatible. There's not difference only in termination, there's difference also in voltage levels on CANH and CANL pins.

What do you mean by "method to test Low speed CAN"?

Regards,

Lukas

[abhishekks]

Dear Lukas,

1) We are going to do only a bare minimal test of CAN lines and CAN transceivers and this will be only one time testing to check the assembly quality and Components. Do we need to consider the Voltage levels for it, also let us know what if impedance is not achieved as per datasheet?

2) On the production line, we are going to test all the interfaces of our Device. We are looping HS_CAN1 and HS_CAN2 physical layers and testing these lines.

In the same way, please suggest how can we test LS_CAN circuitry ( only 1 LS CAN interface available per board). Does NXP uses any Adapters to test the LS CAN transceivers.

Regards,

Abhishek

[lukaszadrapa]

Hi Abhishek,

of course, you need to consider the voltage levels. These are simply two different physical layers and they are not compatible. Here I found some diagrams which show the difference regarding the voltage levels:

https://upload.wikimedia.org/wikipedia/commons/thumb/1/1a/ISO11898-2.svg/800px-ISO11898-2.svg.png?15... 

https://upload.wikimedia.org/wikipedia/commons/thumb/4/44/ISO11898-3_Waveform.svg/800px-ISO11898-3_W... 

To test the transceiver, second node is usually needed. It depends on your setup - it can be some universal CAN tester.

Regards,

Lukas