LS1046A PDN design

[Nareshvarikuntla]

Dear NXP,

I would like to optimize decoupling capacitor around LS1046A. Please let me know the instantaneous  current profile drawn by LS1046A.

Also it would be nice if you can share documents related LS1046A PDN design.

Regards,

Naresh V.

[Bulat]

We do not have such a "current profile".

Please take a look at AN5252 application note ("Design checklist", can be found on our web site), its section 4 provides power design recommendations.

Regards,

Bulat

[Nareshvarikuntla]

Dear NXP,

I have already gone through AN5252. It doesn't have information on current profile and that is why I raised query in this forum.

NXP reference board has 8 layer. But I will be using board with more than 10 layers. In that I will allocate pair of layers for embedded capacitance so that I can reduce the decoupling capacitors and improve the component density.

So for this , I need the instantaneous current drawn by each power supply and their current profile. This information is missing in that datasheet or any other application notes.  Kindly share this information.

Also please do let me know how NXP decided on on number of decoupling capacitors and placement of capacitors for reference board. Kindly share relevant information.

[Bulat]

As I already wrote, we do not have documents with 'current profile'.

To estimate current consuming by the cores and I/O interfaces, you can refer to data sheet. Tables 7 and 10 provides power numbers.

If you take a look at the AN5252, you could find our recommendations about number of decouplng capacitors and their placement. Search for 'General Power supply decoupling' section.

Regards,

Bulat

[Nareshvarikuntla]

Dear NXP,

Please do let me know how decoupling capacitors for LS1046RDB decided. Please share the simulations and Notes.

I believe this information will be available at least with the LS1046RDB board designer. Please share the information.