Hello,
For the design of our product, we are using your CPU with the part number MIMX8UD7DVP08SC. We have chosen to use LPDDR4 (K4F6E3S4HM-MGCJ) memory and the PCA9460A PMIC.
Since we require a voltage level of 1.1 V (instead of 0.6 V) for VDDQX_DDR and VDDQ, we removed the U7 (TPS22921) component from your reference design (MCIMX8ULP-SOM) and connected BUCK4_1V1 directly to VDDQ.
Because of this change, we have two questions:
Could this configuration cause any issues with LPDDR4 operation?
If it does not cause issues, we do not plan to power any peripherals from the LDO1 rail. In that case, can the pins B6 (INL1) and A6 (LDO1) on the PCA9460A be left unconnected?
Also, is it possible to request a review of our schematics by your engineering team?
Thank you in advance for your support.
Best regards,
Zelimir
