LDMOS Bias Sequence

[kinderwood]

What is the proper bias sequence for RF LDMOS transistors?  Specifically I am using the AFM907N.  Does it matter if the gate or drain is applied first?  I am first applying 0V on the gate, then applying drain voltage, then increasing gate to achieve the desired IDq.

[LPP · Accepted solution]

In a well designed, stable circuit, the LDMOS is sequencing indifferent. One can bring up the RF, Gate and Drain tabs in any sequence and the part will amplify as originally intended. A designer must check that the design remains stable in power transient conditions.

In the case of NXP reference circuit, the quiescent currents is determined by separate gate voltage supply. The recommended quick start sequence prevents possibility of unwanted high drain current when the gate supply voltage is too high and if it starts before the drain supply.

Have a great day,
Pavel
TIC

[Sam_hua]

Hello Pavel:

Great to get your suggestion about LDMOS BIAS sequence.

Could you share more details about "recommended quick start sequence prevents possibility of unwanted high drain current", where can I find this recommendation? or which part datasheet mentioned this matter?

Thank you very much!