KW45B41Z83AFT Consultation on Minimum System Design Issues

[Lu888]

Hi experts,

  I am designing a minimum system to operate the KW45 CM33 Main Core 1MB flash using the SWD protocol. Attached is the schematic diagram of the PCB. I would like to inquire if there are any issues with the PCB design or how to design the power supply system for this chip.

  Looking forward to receiving your reply！

  Thanks.

[Christine_Li]

Hi, @Lu888 

Thanks for creating case to us.

For the Hardware Design Considerations for KW45B41Z and K32W148 Bluetooth LE Devices, please refer to our AN13227.

And we also have design files of KW45B41Z-EVK for your reference.

Here is the download link:

https://www.nxp.com/webapp/Download?colCode=KW45B41Z-EVK-DESIGNFILES

For your PCB schematics, I need more time to check.

Best regards,

Christine.

[Christine_Li]

Hi, @Lu888 

For the PCB design, could you please refer our design files of KW45B41Z-EVK?

Do you still need to review your PCB, I checked your PCB schematics, there are too much differences with our design files.

If you need further support, please help to point out which detailed part. Usually, I think just follower our design files should be ok.

Best regards,

Christine.

[Lu888]

Hi,@Christine_Li

I have already referred to your design files of KW45B41Z-EVK,but I still want to ask how to design the power supply.

Best regards.

[Christine_Li]

HI, @Lu888 

The power management and power configuration is on the page 3 of this file: SPF-50555_E.pdf inside of KW45B41Z-EVK-DESIGNFILES\X-KW45B41Z-EVK_E\PDFs. After decompressed the KW45B41Z-EVK-DESIGNFILES.zip, you can find our schematic pdf file.

If you have any questions on our schematic file, please just point your question.

"How to design" is a too big topic. I can only tell you refer to our design files.

If you have detailed question on the schematics, it will better to further discuss.

Best regards,

Christine.

[Lu888]

Hi,@Christine_Li

The VDD_IO_D I power supply for 3.3V,but the VDD_SYS unable to output 1.8v,I want to know why this is happening.

Best regards.

[Christine_Li]

Hi, @Lu888 

From our KW45 schematics, we can see that the  JP13 and JP40 are DNP in default. At the same time, -VOUT_SYS/VDD_SYS is connected to our KW45 chip Pin22. It will be powered from chip Pin22.

The LDO_SYS converter generates 1.8 V by default at VOUT_SYS. VOUT_SYS can be used to power VDD_SYS and external components as long as the max ILOAD is not exceeded.

When VOUT_SYS is not use, we recommend to connect to VDD_IO_D.

Note: When the LDO is bypassed, the input and output should be connected together and tied to an external supply that shall not exceed the maximum input voltage for VDD_SYS. The regulator should also be disabled in software.

For details, you can refer to our KW45 datasheet.

Best regards,

Christine.