How to Use the NFC Device（NT3H1101/1201）

Hirotoshi_NAGAO · ‎12-20-2022

Hello　NXP　advisorI am reviewing NT3H1102/1201 datasheet Rev3.3.
LET ME REVIEW CHAPTER 9.8, WRITE AND READ register operation (P37 Register Access Method).

Q1)
Configuration Registers and Session Registers each have 8 register areas,
but is it possible to write continuously or read continuously?

Q2)
What value should the MASK value set during the Write operation relative to the value of REGDAT? Should it be the same value?

Q3)Is there any way for the RF side to know that Vcc is supplied from the device side,
PTHRU_ON_OFF = 1, and SRAM access is enabled?

Let me know.

Best Regards.

Hirotoshi_NAGAO · ‎12-22-2022

Hello Kelly-san

Thanks　for comment.

Q2　not Resolved.

I wanted to confirm that PTHRU_ON_OFF=Enable.

Since what you told me was PTHRU_ON_OFF = Disable I issued a command to enable and read it again, but the PTHRU_ON_OFF bit was not enabled. why..........

Best Regards

Hirotoshi NAGAO

CHINO Corporation.

KellyLi · ‎12-23-2022

Hello @Hirotoshi_NAGAO

For Q2, just as an example, if you want to enable pass-through mode then the value written would be 0x40. Have a try again.

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.

Best regards,
Kelly
Technical Support
NXP Semiconductor

KellyLi · ‎12-22-2022

Hello @Hirotoshi_NAGAO

Please check the red parts:
Q1) Configuration Registers and Session Registers each have 8 register areas, but is it possible to write continuously or read continuously?
FAST_READ command Don't support FAST_WRITE.

Q2) What value should the MASK value set during the Write operation relative to the value of REGDAT? Should it be the same value?
The NTAG I2C plus acknowledges this (A), and waits for one address byte (MEMA), which corresponds to the address of the block of memory within the session register bytes (FEh).
After acknowledgement (A) by NTAG I2C, the bus master/host issues a MASK byte that defines exactly which bits shall be modified by a 1b bit value at
the corresponding bit position.
The below is an example to write session register to disable pass-through mode:
tx_buffer[0] = NTAG_MEM_BLOCK_SESSION_REGS; //NTAG_MEM_BLOCK_SESSION_REGS = 0xFE
tx_buffer[1] = NTAG_MEM_OFFSET_NC_REG; //NTAG_MEM_OFFSET_NC_REG = 0x00
tx_buffer[2] = NTAG_NC_REG_MASK_PTHRU_ON_OFF; //NTAG_NC_REG_MASK_PTHRU_ON_OFF = 0x40
tx_buffer[3] = 0x00;
I2C_SendBytes(address, txbuffer);

Q3)Is there any way for the RF side to know that Vcc is supplied from the device side, PTHRU_ON_OFF = 1, and SRAM access is enabled?
The RF side has no way of knowing the power supply mode. However, if passthrough mode is enabled, SRAM memory access must be powered by VCC.

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.

Best regards,
Kelly
Technical Support
NXP Semiconductor

Hirotoshi_NAGAO · ‎01-06-2023

Hello　NXP　Support

Thank you for your comments.

Sorry for the late reply due to the year-end and New Year holidays.

Q1）I Understand

Q2）I Understand

Q3) additional Question

When trying to read Byte while changing REGA of Session Register 2 bytes of data is sent only for the first time. Does the master side have to return NAK for each byte received?

refer to Session Register access.pdf

Best Regards

let me know.

Hirotoshi NAGAO

CHINO Corporation

KellyLi · ‎01-08-2023

Hello @Hirotoshi_NAGAO

In the I2C communication protocol ACK or NACK are the Behavior of the slave, so the master would not return NACK or ACK.

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.

Best regards,
Kelly
Technical Support
NXP Semiconductor

Hirotoshi_NAGAO · ‎01-10-2023

Hello 　　Kelly-san

Thank you for your comment.

I don't think so,

Session Reg access is on a Byte basis.

The master is the MCU and the slave is NT3H1201, and in the Read operation after the Reg Number is set, the 0x01 is transferred first, followed by the 0xFF. If the master side does not respond to the NAK immediately after receiving the first 0x01 from Slave, subsequent 0xFF (garbage data) will be sent.

I thought that the behavior of 1) was appropriate, but if I didn't do 2), I would receive garbage data. Is it correct to understand that it is necessary to accurately notify NAK on the master side in order to perform 1-byte read with the NT3H1201 as a slave?

1) Does the NT3H1201 on the SLAVE side set Stop Condition after BYTE transfer and send subsequent data?

2) Whether to respond NAK after reading 1 BYTE on the MASTER side was not understood.

Thanks

Best Regards.

Let me know.

Hirotoshi NAGAO

CHINO Corporation

KellyLi · ‎01-10-2023

Hello @Hirotoshi_NAGAO

Please check the below figure that is for NTAG I2C PLUS READ operation.

If you still have questions, please refer to page 45 of Datasheet, it may be helpful for you.

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.

Best regards,

Kelly

Technical Support

NXP Semiconductor

Hirotoshi_NAGAO · ‎01-11-2023

Hello Kelly.

The method you showed is a READ and WRITE Operation.

What I am confirming and asking is the NT3H1201's WRITE & READ Register Operation, not the I2C Plus and WRITE and READ Operation. NT3H1101/NT3H1201 Product data sheet Rev3.3 15 Jul 2015 is confirmed. In the case of the NT3H1201 Session Register, it is not READ and WRITE Operation (P35). It should be READ and WRITE Register Operation (P37).

Best Regards

let me know.

Hirotoshi NAGAO

CHINO Corporation

KellyLi · ‎01-11-2023

Hello @Hirotoshi_NAGAO

NTAG I2C plus is fully compatible with NTAG I2C. And the former has all features of the latter. Actually, the operation of reading and writing registers is the process of reading and writing I2C. The below screenshot is an example for read session register for your reference. Hope to help you.

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.

Best regards,

Kelly

Technical Support

NXP Semiconductor