How P3A9606JK Works

[vanpham]

Hi NXP team,

I have already read the datasheet of P3A9606: P3A9606JK - Dual bidirectional I3C/I2C-bus and SPI voltage-level data sheet

The IC can support push pull and open drain applications. As the 13.1 Applications section, I can know how to connect Master to I2C or I3C devices.

I just know if the input is push-pull then the output is push-pull according to the corresponding voltage of the 2 sides (i.e. according to the example: the input is push-pull 1.2V then output is push-pull 1.8V) and vice versa if the input is open-drain, then the output is open drain.

Can you explain in detail how P3A9606JK can work? How does the P3A9606JK know when it's push pull and when it's open drain so it can handle it properly? It has a detector, right? Based on block diagram, I cannot explain how it works properly.

And besides datasheet, do you have any documents about P3A9606JK?

Thank you.

P3A9606JK-EVB 

[vanpham]

Hi Tomas,

Thanks for your explanation.

I have some unclear information.

Q1: For Open-drain mode: When a port translates from high-to-low (i.e., the master/slave driver pulls a pin low), is there a combination both Fall Accelerator and FET pass-gate to accelerate falling edges in P3A9606JK. Or just having FET pass-gate without accelerating falling edges (i.e. falling time depend mainly on drive strength of master/slave driver)? I would like to know both fall accelerator and rise accelerator will not be used or just rise accelerator is not used in open drain mode (rise time depends on external pull-up resistors as you explained).

Q2: For Push-pull mode: As I understand, both rise accelerator and fall accelerator on A and B ports are be used.

For e.g.: When generating a transaction from A port to B port of P3A9606JK 

+ Translate from high-to-low (device pulls low): Falling edge will be detected by Fall Accelerator at A port of P3A9606JK and at the same time, FET pass-gate will be turned on then Fall Accelerator at B port also detect falling edge of A side and fall time will be accelerated by both Fall Accelerator of A and B ports.

+ Translate from low-to-high (device pulls high): Rising edge will be detected by Rise Accelerator at A port of P3A9606JK and somehow (maybe there is a detector or a controller ??) to activate Rise Accelerator at B port. So rise time will be accelerated by both Rise Accelerator of A and B ports.

Can you correct me if my understand is wrong?

Thank you.

[TomasVaverka]

Hi Van,

Your understanding is correct. In open-drain mode, the fall accelerator is used, rise accelerator not. In push-pull mode, both fall and rise accelerators are used.

BRs, Tomas

[vanpham]

Hi Tomas,
Thank you so much.

[TomasVaverka]

Hi Van,

Yes, the P3A9606JK has detection logic, but not a "detector" block like you could see in some block diagrams. Instead, it uses a clever analog pass-gate mechanism combined with edge-rate accelerators to sense and react automatically to the type of signal being applied.

The core of the P3A9606JK’s logic is an N-channel FET pass-gate between the A and B sides. This pass-gate is enabled only when the signal on one side is Low, allowing the Low signal to propagate to the other side. When both sides are High, the pass-gate turns off, preventing any short between different supply domains.

Edge-rate accelerators help with transition detection (e.g. falling edge of a push-pull signal). They sharpen the signal edges, making it more compatible with high-speed buses like SPI and I3C.

Open-drain: Only Low is actively driven. High relies on pull-ups. The device sees the line floating and uses its internal logic to not drive the output - it just passes the Low through when detected.

Push-pull: Actively drives both High and Low. As explained before, the translator uses edge detection and pass-gates to replicate the push-pull transitions on the other side (at the translated voltage).

As of now, there is no dedicated application note specifically for the P3A9606JK. 

BRs, Tomas