GD3162 gate driver

[Akshat_VE02376]

Hi NXP,
This is regarding the MODE2 register of gate driver 3162. What exactly is the correct way of writing to this mode 2 register? In our project we have observed several challenges in writing to this register:
1.When using unions to write to the MODE2 register bits, we are unable to write to this register

2.Now I'm writing directly the required value to this register after entering Configuration mode by setting CONFIG_EN to 1. Then in the data frame to be written, I'm keeping the CONFIG_EN bit as zero while writing. 

Now, that we are planning for BIST, this behavior of MODE2 can cause some issues. Please clarify what is the correct way of performing the write operation to this register.
This is the code snippet of my function :

FUNC (uint8, GD_CODE) GD316xCdd_Config_DaisyChain(void)

{

    uint8 GD316xCdd_ReturnStatus = E_NOT_OK;

    uint16 GD316xCdd_rxData[GD316xCdd_DEVCOUNT] = {0u}; /**< Buffer to store received SPI data */

    /* Initialize register settings to default values */

    GD316xCdd_mode1_settings.GD316xCdd_Data              = GD316xCdd_MODE1_DEFAULT_VALUE;

    GD316xCdd_mode2_settings.GD316xCdd_Data              = GD316xCdd_MODE2_DEFAULT_VALUE;

    GD316xCdd_config1_settings.GD316xCdd_Data            = GD316xCdd_CONFIG1_DEFAULT_VALUE;

    GD316xCdd_config2_settings.GD316xCdd_Data            = GD316xCdd_CONFIG2_DEFAULT_VALUE;

    GD316xCdd_config3_settings.GD316xCdd_Data            = GD316xCdd_CONFIG3_DEFAULT_VALUE;

    GD316xCdd_config6_settings.GD316xCdd_Data            = GD316xCdd_CONFIG6_DEFAULT_VALUE;

    GD316xCdd_config7_settings.GD316xCdd_Data            = GD316xCdd_CONFIG7_DEFAULT_VALUE;

    GD316xCdd_configAout_settings.GD316xCdd_Data         = GD316xCdd_CONFIGAOUT_DEFAULT_VALUE;

    GD316xCdd_statusMask1_settings.GD316xCdd_Data        = GD316xCdd_MSK1_DEFAULT_VALUE;

    GD316xCdd_statusMask2_settings.GD316xCdd_Data        = GD316xCdd_MSK2_DEFAULT_VALUE;

    GD316xCdd_reportMask1_settings.GD316xCdd_Data        = GD316xCdd_RMSK1_DEFAULT_VALUE;

    GD316xCdd_reportMask2_settings.GD316xCdd_Data        = GD316xCdd_RMSK2_DEFAULT_VALUE;

    GD316xCdd_OverTempThresh_settings.GD316xCdd_Data     = GD316xCdd_OT_TH_DEFAULT_VALUE;

    GD316xCdd_OverTempWarnThresh_settings.GD316xCdd_Data = GD316xCdd_OTW_TH_DEFAULT_VALUE;

    /* MODE1 register configuration */

    GD316xCdd_mode1_settings.Bits.GD316xCdd_AOUT      = GD316xCdd_MODE1_AOUT_TEMP_AND_SEC_QTY;

    GD316xCdd_mode1_settings.Bits.GD316xCdd_DSCH_CNTL = GD316xCdd_MODE1_DSCH_CNTL_PWM_FSSTATE;

    /* CONFIG1 register configuration */

    GD316xCdd_config1_settings.Bits.GD316xCdd_VCCUV_LATCH = GD316xCdd_CONFIG1_INTB_DISABLES_PWM;

    GD316xCdd_config1_settings.Bits.GD316xCdd_VCCUV_TH    = GD316xCdd_CONFIG1_UV_TH_10_0V;

    /* CONFIG3 register configuration */

    GD316xCdd_config3_settings.Bits.GD316xCdd_INTBFS = GD316xCdd_CONFIG3_INTB_INDICATES_FSENB_LOW;

    /* CONFIG6 register configuration */

    GD316xCdd_config6_settings.Bits.GD316xCdd_RTMONDLY = GD316xCdd_CONFIG6_RTMONDLY_2100_OR_1130N;

    GD316xCdd_config6_settings.Bits.GD316xCdd_VCCOV    = GD316xCdd_CONFIG6_VCCREG_18_0V;

    /* CONFIG7 register configuration */

    GD316xCdd_config7_settings.Bits.GD316xCdd_DESAT_TH = GD316xCdd_CONFIG7_DESAT_TH_11_25V;

    /* CONFIGAOUT register configuration */

    GD316xCdd_configAout_settings.Bits.GD316xCdd_AOUT_SEL = GD316xCdd_CONFIGAOUT_SEL_DESAT;

    /* MSK1 register configuration */

    GD316xCdd_statusMask1_settings.Bits.GD316xCdd_GSERRM = GD316xCdd_MSK1_Fault_NOT_MASKED;

    /* Enter configuration mode */

    GD316xCdd_ReturnStatus = GD316xCdd_Config_En_DaisyChain(TRUE);

    GD316xCdd_Config_Sts = TRUE;

    /* Writing configurations to GD316x registers */

    GD316xCdd_ReturnStatus = GD316xCdd_Wr_Reg_DaisyChain(GD316xCdd_spiAddrMode1, GD316xCdd_mode1_settings.GD316xCdd_Data);

    GD316xCdd_ReturnStatus = GD316xCdd_Wr_Reg_DaisyChain(GD316xCdd_spiAddrConfig1, GD316xCdd_config1_settings.GD316xCdd_Data);

    GD316xCdd_ReturnStatus = GD316xCdd_Wr_Reg_DaisyChain(GD316xCdd_spiAddrConfig3, GD316xCdd_config3_settings.GD316xCdd_Data);

    GD316xCdd_ReturnStatus = GD316xCdd_Wr_Reg_DaisyChain(GD316xCdd_spiAddrConfig6, GD316xCdd_config6_settings.GD316xCdd_Data);

    GD316xCdd_ReturnStatus = GD316xCdd_Wr_Reg_DaisyChain(GD316xCdd_spiAddrConfig7, GD316xCdd_config7_settings.GD316xCdd_Data);

    /* Enter normal run mode */

    GD316xCdd_ReturnStatus = GD316xCdd_Config_En_DaisyChain(FALSE);

    /* Reading and clearing fault status registers */

    GD316xCdd_ReturnStatus = GD316xCdd_Rd_Status1_DaisyChain(GD316xCdd_rxData);

    if ((GD316xCdd_rxData[0] > 0) || (GD316xCdd_rxData[1] > 0) || (GD316xCdd_rxData[2] > 0) ||

        (GD316xCdd_rxData[3] > 0) || (GD316xCdd_rxData[4] > 0) || (GD316xCdd_rxData[5] > 0))

    {

        GD316xCdd_ReturnStatus = GD316xCdd_Wr_Status1_DaisyChain(GD316xCdd_SPI_REG_DATA_MASK);

        GD316xCdd_ReturnStatus = GD316xCdd_Rd_Status1_DaisyChain(GD316xCdd_rxData);

    }

    GD316xCdd_ReturnStatus = GD316xCdd_Rd_Status2_DaisyChain(GD316xCdd_rxData);

    if ((GD316xCdd_rxData[0] > 0) || (GD316xCdd_rxData[1] > 0) || (GD316xCdd_rxData[2] > 0) ||

        (GD316xCdd_rxData[3] > 0) || (GD316xCdd_rxData[4] > 0) || (GD316xCdd_rxData[5] > 0))

    {

        GD316xCdd_ReturnStatus = GD316xCdd_Wr_Status2_DaisyChain(GD316xCdd_SPI_REG_DATA_MASK);

        GD316xCdd_ReturnStatus = GD316xCdd_Rd_Status2_DaisyChain(GD316xCdd_rxData);

    }

    return GD316xCdd_ReturnStatus;

}

[JozefKozon]

Hi Akshat,

please download and check the GD31xx Driver Example Code for your reference. You can download it from the GD3162 product page, under the Software section.

In the example code, indeed extern union is used to write to Mode2 register. Please test the code and see if it will work for you. 

With Best Regards,

Jozef

[Akshat_VE02376]

Hi Jozef,
I already have this example code, but here mode2 is only used for unlocking the write operation by setting the CONFIG_EN bit to 1...There is no additional configuration/s done for MODE2. In my project I need to do other bit configurations for this register which is causing issue if I'm writing it in the same way in which other registers are written

[JozefKozon]

Hi Akshat,

the issue might be not caused by the writing, but by the BIST you mentioned. Please download and refer to Errata sheet ER1. There is description of the BIST running issue and also a workaround. Please download the Errata sheet from the GD3162 product page, under the Secure section.

With Best Regards,

Jozef