Dear NXP Team,
I would like to ask some questions about disabling interrupts and cache management when using the FlexSPI ROM API. I am using the RT1170 chip with FreeRTOS. Occasionally, the system hangs, and I suspect it may be caused by Flash operations using the ROM API.
1. In the SDK example `flexspi_romapi_cm7`, when reading/writing/erasing Flash with the ROM API, there is no interrupt disable/enable operation. I also found a document titled *"i.MX RT series FlexSPI Nor ROM APIs Usage & Flashloader.pdf"*, which mentions interrupts:
Is it because the ROM API already handles interrupt masking internally, or is there another reason?
To implement write and erase operations at arbitrary Flash addresses, I have wrapped the ROM API into `flash_eraseData()` and `flash_writeData()` functions, and simply wrapped the read operation as `flash_readData()`:
Could you please review whether there are any potential errors in my three wrapper functions(I am a bit doubtful whether an erase operation is required before calling ROM_FLEXSPI_NorFlash_ProgramPage)? Also, when calling these functions (not the ROM API directly), is it necessary to disable/enable interrupts?
2. In the SDK example, after calling `ROM_FLEXSPI_NorFlash_ProgramPage` to write Flash, there is a `DCACHE_InvalidateByRange` operation to invalidate the D-Cache.
I understand that the ROM API operates on external NOR Flash through the FlexSPI controller's programming sequence, bypassing the Cache, so the CM7's data cache lines are not automatically updated.
Later, when we use `memcpy` to access Flash data, the access goes through D-Cache, and stale values may be fetched if the cache hits. Therefore, invalidating the D-Cache is necessary.
In my three wrapper functions that use these ROM APIs, could there also be cache coherency issues due to improper handling?
Any help would be very appreciated.
Best regards,
langya.
