Hello and thanks in advance,
I was looking for DDR4 skew numbers (for length matching on their PCB) as per a customer's request in regards to a design involving the LS1046A and I ended up on Chapter 3.9 of the LS1046A datasheet which explains the timing for SDRAM.
I was wondering if there is additional documentation for this aspect and I thought that finding some reference on the LS1046A could point out to this design rule with Layerscrape.
could it be possible to share some design guidelines for DDR4 with LS1046A if there is any available? (unfortunately I do not have access to additional documentation from Docstore).
Best Regards,
