DDR Init Failed

[srinivasa]

Hi,
We are using 16GB DDR 4 sodimm module.
We have observed DDR booting inconsistency issue in one of the board.
We suspected issue could be board timing issue and changed RC values of board timing  structure as below, but still same issue seen on this board.

static const struct board_timing udimm[] = {
//  {0x03, rce, 0x01020204, 0x04040403}
  {0x0F, rce, 0x01020204, 0x04040403}  //changed from 0x03 to 0x0F
};

DDR boot failed logs:
[ 19.682701] reboot: Restarting system
NOTICE: UDIMM D41.23286S.001
ERROR: Found training error(s): 0x2100
ERROR: Error: Waiting for D_INIT timeout.
ERROR: Writing DDR register(s) failed
ERROR: Programing DDRC error
ERROR: DDR init failed.
NOTICE: Incorrect DRAM0 size is defined in platform_def.h
ERROR: mmap_add_region_check() failed. error -22
ERROR: mmap_add_region_check() failed. error -22
NOTICE: BL2: v2.4(release):la12xx-sdk2.1-0-gb07d2b6c9-dirty
NOTICE: BL2: Built : 21:16:51, Jun 30 2023

Could you please let us know any inputs on this, is it RC_Timing, DDR Calibration values issue?

[khushbur]

Hi @srinivasa 

Please refer to below link  to modify Plat/nxp/<SOC>/<Board>/platform_def.h and Plat/nxp/<SOC>/<Board>/ddr_init.c according to your target board.

https://docs.nxp.com/bundle/GUID-487B2E69-BB19-42CB-AC38-7EF18C0FE3AE/page/GUID-903DCB6A-FA4B-4A1C-B...

The DDR driver supports the following board level applications for DDR:
• DIMM: Driver reads SPD for configuring DDR timing parameters
• Mock DIMM: Hardcoded timing in place of reading SPD
• Discrete DDR: Driver requires a static DDR configuration to be added

Please choose one DDR initialization method in the above for your target board.

In addition you need to use QCVS tool to calculate the initial DDR initialization parameters according to the DDR data sheet(or reading from SPD), then use DDRv tool to do validation and optimization.

Thanks

Khushbu