Clarification need in SBC FS0B Implementation

[Sivahari]

Hi NXP,

I am using SBC Chip(MFS2613AMDA6) for Some Failsafe action feature in my project.

I have gone through the datasheet. It is mentioned that FS0B Pin will be low at initial power on condition and it will be released to high, once release sequence command send through SPI.

But still I need some more clarity in FS0B internal circuit, since it is released to high before writing release sequence command through SPI.

Please explain when this MOSFET will be switched on to pull down the FS0B pin state to low.

Thanks for Support.

[guoweisun]

No sure for fully understand your questions.

This FS0B internal structure controlled by function safety center ,after power on reset it will back to default value FS0B LOW, which need release it to high before enter into normal mode for better to monitor the system safety function.

[Sivahari]

Hi Guoweisun,
Thanks for the reply.
Let me make my question clear.
As you said, FS0B pin default value is low after power on reset. But in my project, FS0B pin is high after power on reset.
I saw FS0B circuit implementation in datasheet. There is a MOSFET connected with FS0B pin.
So, Is there any way to control the MOSFET to stay FS0B low states after power on reset condition?

[guoweisun]

Did you disconnect the FS0B with the external signal? you can disconnect it with external circuit then test again.