Hello,
Sorry for the delay in replying.
Please see my observations below:
1. RFin and RFout : Cin and Cout are stated as 18 pF and 3.9pF. The values of C1 and C2 are critical for power on/off settling time. When the value for those capacitors is increased significantly the switching speed is affected. In your Schematic these capacitors are 20pF and 4pF.
2. Vcc1 and Vcc2 : In NXP Reference design C6, C11 and C4, C12 decoupling capacitors respectively bypass VCC1 and VCC2.

C4 and C6 preferably should be located as close as possible < 1 mm to the device, to avoid AC leakage via the bias lines.
In your case these capacitors are C3 and C2 for VCC1 but I do not see decoupling capacitors for VCC2.

In your PCB these capacitors are not located as close as possible.

3. Proper grounding of the GND: I recommend connecting N.C. pins to GND to improve the thermal dissipation.
4. Enable: To limit the current, a 5.6 kΩ resistor can be used in series.
You can check this information in the application note AN13844 https://www.nxp.com/docs/en/application-note/AN13844.pdf
Hope this helps!