Hello, I am attempting to use the AFIC901N 2 stage amplifier at 220 Mhz. I have replicated the 136-174 Mhz broadband reference circuit from datasheet on my board. I have scaled L and C values from the 155 Mhz center frequency to 220 Mhz. After some time the gate-to-source shorts to a few 10's of ohms. Has happened to both first and second stages at times. I suspect it may be the ESD input protection diodes being overstressed but not sure. Running from 7.5V source and setting bias current set as specified in datasheet. Something breaking into oscillation? I am looking for ideas to solve the failures.
Solved! Go to Solution.
It is unlikely that the reason is related to ESD input protection diodes being overstressed.
Typical failure mechanisms observed on LDMOS are the silicon 'pit' and the 'fused' drain metal runner.
The end result for a MOSFET device (such as LDMOS) is that at least two if not all three of the terminals (drain, gate, source/body) are electrically shorted together (applicable to RF PA MMIC as well).
The silicon pit is associated with an over-voltage triggering a bipolar snapback. The fused drain runner is associated with thermal damage from repeated avalanche.
Both failure mechanisms have avalanche breakdown as a precondition for failure.
Drain voltage VDS = Vbias + Venv + Vlfres + Vswr
Vbias supply voltage
Venv envelope of RF signal
Vlfres low frequency resonance
Vswr load mismatch reflected voltage
Main Contributors to Application Fail:
Intrinsic die breakdown voltage
Bias modulation via IM2 envelope
Transient behavior – bias feed inductance
Instability - Oscillations
RF Reflections – VSWR
Very low resonance frequencies – insufficient bulk capacitance
Input Signal Bandwidth – Signal rise times
Severe Input Overdrive
Each reason may cause transient over-voltage and then the fail. You should check your design against them.
Let me explain shortly some of the issues:
- At low frequency, the drain feeder is inductive and the device is capacitive. This results in a resonant network. At the resonance frequency (typically about dozen MHz), the die is loaded by a very high impedance. This results in a drain voltage modulation. If the signal bandwidth is wider than resonance frequency, the output IM2 products may cause envelope modulation at resonance. Suggestion is to redesign bias feed so that the resonance frequency is higher than bandwidth of the signal.
-Input Signal Bandwidth – Signal rise times. If the RF ramp of the signal is not properly controlled, the signal will cause ringing in the bias feed circuitry saturating the PA. Basically, it is the same issue as above but the reason is high bandwidth of the signal with short rise/fall time. By properly controlling the ramp time of the modulator, the overshoot can be eliminated preventing PA saturation.
-Gate voltage overdrive. Gate voltage exceeds the specified safe operating voltage resulting in gate leakage or gate shorts from the gate oxide damage. Input overdrive can occur when device is not protected from oscillation, feedback coupling, or other transient voltage peaks.
Have a great day,
Pavel
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It is unlikely that the reason is related to ESD input protection diodes being overstressed.
Typical failure mechanisms observed on LDMOS are the silicon 'pit' and the 'fused' drain metal runner.
The end result for a MOSFET device (such as LDMOS) is that at least two if not all three of the terminals (drain, gate, source/body) are electrically shorted together (applicable to RF PA MMIC as well).
The silicon pit is associated with an over-voltage triggering a bipolar snapback. The fused drain runner is associated with thermal damage from repeated avalanche.
Both failure mechanisms have avalanche breakdown as a precondition for failure.
Drain voltage VDS = Vbias + Venv + Vlfres + Vswr
Vbias supply voltage
Venv envelope of RF signal
Vlfres low frequency resonance
Vswr load mismatch reflected voltage
Main Contributors to Application Fail:
Intrinsic die breakdown voltage
Bias modulation via IM2 envelope
Transient behavior – bias feed inductance
Instability - Oscillations
RF Reflections – VSWR
Very low resonance frequencies – insufficient bulk capacitance
Input Signal Bandwidth – Signal rise times
Severe Input Overdrive
Each reason may cause transient over-voltage and then the fail. You should check your design against them.
Let me explain shortly some of the issues:
- At low frequency, the drain feeder is inductive and the device is capacitive. This results in a resonant network. At the resonance frequency (typically about dozen MHz), the die is loaded by a very high impedance. This results in a drain voltage modulation. If the signal bandwidth is wider than resonance frequency, the output IM2 products may cause envelope modulation at resonance. Suggestion is to redesign bias feed so that the resonance frequency is higher than bandwidth of the signal.
-Input Signal Bandwidth – Signal rise times. If the RF ramp of the signal is not properly controlled, the signal will cause ringing in the bias feed circuitry saturating the PA. Basically, it is the same issue as above but the reason is high bandwidth of the signal with short rise/fall time. By properly controlling the ramp time of the modulator, the overshoot can be eliminated preventing PA saturation.
-Gate voltage overdrive. Gate voltage exceeds the specified safe operating voltage resulting in gate leakage or gate shorts from the gate oxide damage. Input overdrive can occur when device is not protected from oscillation, feedback coupling, or other transient voltage peaks.
Have a great day,
Pavel
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------