ABOUT FREESCALE AFT09S282NR3 OPERATING CONDITION

[313330546]

To whom may concern,
I use AFT09S282N Transistor from NXP (formerly from Freescale) to achieve 53.5dBm (equals to 225Watts) RF peak power in Pulse mode in my transmitter module with the following pulse specifications:
Pulse Width: 250 μsec
Pulse Repetition Interval: 1250 μsec
Using the above parameters the average RF Output power is 45Watts which has a great back off from the transistor maximum average power which is 80Watts as reported at the transistor datasheet Rev. 0, 10/2012.
I have mounted the transistor on a brass carrier (or copper carrier) as a flange and the module is well cooled so the final flange temperature of the transistor is about 70° Celsius at 225W RF peak output power.
The operating working frequency is about 850MHz and the matching networks are realized on a 0.02” Rogers RO4003 PCB.
Gain, Output power and efficiency seems to be normal due to ADS simulations (using the large signal model published by NXP) and my measurements on the module.
The problem is that after continuous operation (several days for example) of my module, the transistors begin to fail on several modules. The transistor gate becomes short circuited.
My questions:
1. Is this transistor suitable for my pulse condition (250μsec/1250μsec) with 225W RF peak power and 45W RF average power?
2. Is 70° Celsius suitable for long term operation of this transistor?
Any additional guidance and recommendations will be appreciated.
Sincerely yours.

[LPP]

1. This transistor can be used in your pulse condition.

2. 70° Celsius case temperature is suitable for long therm operation.

I think, you problem is not thermal management related but caused by electric overstress.

EOS occurs when the maximum voltage potentials have been exceeded across any two terminals of the device inducing device breakdown resulting in excessive currents.

AFT09S282N maximum drain-source voltage is 70V. Most probably this parameter is violated in your design.

Typical reasons of EOS for pulse mode are:

(a) bias feed inductance determines minimum rise/fall time of the signal.

L*dI/dt < Vdss, dt > L*dI/Vdss.
Suppose, bias L = 100nH, Vdss = 70V, dI=10A (for 280W) -> dt > 14ns

It is reasonable to decrease bias inductance. So, if L=5nH -> dt > 0.7ns. It would not cause a problem.

(b) Very low resonance. Bias feed inductance and output capacitance cause resonance at low frequency. If the ramp of the signal is not properly controlled, the signal will cause ringing in the bias feed circuitry and may cause overstress.

By properly controlling the ramp time of the RF signal, the overshoot can be eliminated. RF rise time should be more than 1/F_low_resonance.

Also, it is possible to shift up low resonance frequency by using two bias feed lines (doubles resonance frequency) and/or using shortened feed lines to decrease feed line inductance at low frequency.

(c) RF Reflections – high VSWR. 
Have a great day,
Pavel
NXP TIC

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[313330546]

Hi, thank you for your reply and great guidance.

I have some more questions if possible:

1.       Due to your experience if EOS violated in my design due to any reasons you mentioned (a: bias feed inductance) or (b: very low resonance), does this violation damage the transistor at once or may take time to damage it? Because in my transmitter modules I have some failed transistors after several days of continuous operation (24 hour pulse operation).
2.       The original matching network of this transistor provided by its datasheet (Rev. 0, 10/2012) is tuned for 920-960MHz frequency band. I have changed some capacitor values to shift the frequency band to 800-900MHz and no change in transmission lines. The final matching networks are shown in figure (1) which are implemented on Rogers 02” RO4003 PCB.

Due to the details provided above, and due to this point that I have not changed the transmission lines dimensions and characteristics compared to the original evaluation board presented in the datasheet, and due to about 40nsec rise time of the RF signal, is there any chance to the EOS problem?

1.       We have another problem that we think it can have some kind of relation to our main problem which is damaging some transistors after long term operation. To DC biasing of the transistor we adjust the gate voltage to drain 1.4A (normally about 08V ~ 2.15V). After the long term operation of the transmitter module under pulse condition the bias current increases to 1.75A ~ 2A with no change in the gate voltage. It means that the bias current is increased about 350mA to 600mA with no change in gate voltage. Of course all measurementsare done under the same condition such as load termination, temperature, etc. In these cases we should decrease the gate voltage about 40mV to 80mV to achieve the previous 1.4A. We think that theses transistors (with increased bias current)are going to fail in near future under continuous operation condition although we have readjusting the bias current to 1.4A. Also we have some transistors that have been working in the same condition but no increase in bias current has occurred.
2.       I use two types of modulations inside the transmitting pulse: (a) Linear Frequency Modulation (LFM), (b) BPSK modulation. Is there any evidence that these modulations can increase the potential of EOS or any kind of other damage to AFT?

Sincerely yours.

[313330546]

Hi, thank you for your reply and great guidance.

I want to send you my private design with some questions would you plz tell me your emaild?