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Contributor I


the recent weeks I've written NTAG I2C drivers for a new Cortex M4 MCU. Beside one issue everything works well.

The one tricky thing is how to get the SRAM_I2C_READY and the SRAM_RF_READY to be set to 1b. According to the spec sheet this should happen automatically considered PTHRU_DIR is defined and PTHRU_ON_OFF is set to 1b.  Also the FD pin is activated.

All this is done, all this works, but when the MCU writes to the SRAM, or the Reader writes the the SRAM the respective SRAM_I2C_READY or SRAM_RF_READY never get set to 1b. 

In PASS_THROUGH_MODE the SRAM gets activated in sector 1 and gets reduced to 16bytes overall. From F0 to FF.  So, I have written one page to the SRAM from the RF side. I've also tried it with writing the whole block in a go to the SRAM from the RF side but SRAM_I2C_READY never gets set to 1b.

Any help appreciated.

Tom Fuerstner

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NXP Employee
NXP Employee

The size of the SRAM in NTAG I2C is not 16 bytes, but 64 bytes. From NFC side it is mapped as 16 pages, 4 bytes each. From I2C side it is mapped as 4 blocks, 16 bytes each.

The SRAM_I2C_READY bit is only set after writing to the terminator page from the NFC side, i.e. page FF (last 4 bytes). See the next illustration from datasheet:


The attached presentation can also bring clarity about Pass-through mode.


Jorge Gonzalez

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