NXP NFC NT2H2111 PASS THROUGH Malfunction Problem

[jwon]

Hello, this is Jae-won.

NFC data writing is done through PASS-THROUGH SRAM.

NFC PASS-THROUGH SRAM WRITING problem occurred in the field.

Although AUTH authentication can be achieved with a smartphone, an abnormal symptom has been found that some products do not access the SRAM area.

I found the difference between not working and working, but I don't understand.

Even if it is not normal ndef data, if there is 0XFE in the NDEF area, it operates normally.

I am attaching some screenshots and code.

I've looked through the datasheet from scratch regarding the PASS-THROUGH SRAM operation, but couldn't find anything about it.
Please check quickly.

SRAM(0XF3) access and/WRITING normal operation memory

Pass-through sram memory (0XF3~) not accessible (products that are currently mass-produced and installed on site) 

Config / Session reg area

When SRAM is not accessed ( 0xEC ED ) Memory contents read from the smartphone
(pass-through sram memory didnot be activated)
Only the values ​​below are kept
29 00 F8 48
08 01 01 00

Memory contents read from smartphone when SRAM is accessed ( 0xEC ED )
After maintaining the value below, sram is accessed normally.
69 00 F8 48
08 01 21 00

[Fabian_R]

Hello sir, we should first perform some tests, we will be very grateful if you could help us.

Please the first format the NTAG I2C device using TAGWriter App, in the Erase option, and then, select NDEF format. This will help us to be sure the tag is working properly. Now, according to the Datasheet, in order to access the SRAM of the NTAG I2C, it is required that the tag is powered via VCC, could you confirm this?

Please keep in mind that from the NFC perspective it is only possible to access if the SRAM is mirrored onto the EEPROM memory space.

Please let us know if you have any questions about SRAM that are boarded in section 8.3.4 of the Datasheet. If you could please share with us the full configuration registers and how are you accessing the mirrored EEPROM it would be great for us to understand what is happening.

[jwon]

hi thank you reply

When the memory of the picture below picture 2

All of the actions below are possible.
1. Session reg read available
2. Protected user memory can read/write
3. UnProtected user memory can read/write
Only PASS-THROUGH is not activated and the SRAM memory area cannot be accessed.

It was confirmed that PATH-THROUGH is not activated when checking ns reg through I2C as well as NFC MOBILE operation.
All conditions (product, environment) under the same circumstances

my code is good working.

i set PASS-THROUGH, but it did not set PASS-THROUGH on  picture 2.

 picture  1 is that I have verified that it works correctly.

static void NT3H2X1_PTHRU_on_off(nfc_driver_t *nt3h2x1,u8 reg_on )

{

                u8 write_data[4], ret,result;

           // pass-through on

           if(reg_on)

           {

                     result = ((1 << NT3H2X11_NC_REG_PTHRU_ON_OFF_SHIFT) & NT3H2X11_NC_REG_PTHRU_ON_OFF_M);

           }

           else

           {

                     result = ((0 << NT3H2X11_NC_REG_PTHRU_ON_OFF_SHIFT) & NT3H2X11_NC_REG_PTHRU_ON_OFF_M);

           }

           write_data[0] = NT3H2X11_I2C_SESSION_REGS_MEM_ADDR;

           write_data[1] = NTAG_MEM_OFFSET_NC_REG; // reg index

           write_data[2] = NTAG_NC_REG_MASK_PTHRU_ON_OFF; // reg mask

           write_data[3] = result; // ns reg index

           ret = nt3h2x1->i2c->write(nt3h2x1->i2c, NT3H_SLAVE_ADDRESS, write_data, 4);

}

picture 1. PATH-THROUGH operation 100%
Please see 00Ch, 00Dh memory.

Memory contents read from smartphone when SRAM is accessed ( 0xEC ED )
After maintaining the value below, sram is accessed normally.
69 00 F8 48
08 01 21 00

picture 2. PATH-THROUGH does not work 100%
Please see 00Ch, 00Dh memory.

When i added like 1 picture (just 2 line) ,  this is working 100%, 

and i back to below . it do not work 100%

When SRAM cannot be accessed ( 0xEC ED ) Memory content read from the smartphone pass-through sram memory cannot be activated
Only the values below are kept
29 00 F8 48
08 01 01 00

PATH-THROUGH is activated according to the data written in eeprom. All other parts (settings) are the same

I can make this  Malfunction Problem always.

[Fabian_R]

Hello sir.

00C and 00D (0xC, 0xD) are User Memory, we need to see the configuration registers, please share with us the content of address: 0x3A for Config Registers. 0xF8 to 0xFB for SRAM and, the session registers 0xFE.

In case you have Passthrough Mode ON, address 0x3A byte 0 should show that Bit 6 is 1, along with this bit, the other configuration Fields should be set as your application needs. For further information, please check Table 13. Configuration Bytes of the NTAG I2C Datasheet

[jwon]

Hello

normally , SRAM access is ok.   Passthrough Mode control is no problem. it is work 100%

But, 

I just erased USER NDEF EEPROM by 00.  SRAM IS NOT WORKING 100%. 

I uploaded   Memory map screenshot from NFC perspective on first post. 

that show 0xE8, 0xE9  memory . 

That is same with 0x3A on I2C interface .  

I set "Passthrough Mode ON " on session register .  i uploaded that code, already on previous post.

static void NT3H2X1_PTHRU_on_off(nfc_driver_t *nt3h2x1,u8 reg_on )

{

                u8 write_data[4], ret,result;

           // pass-through on

           if(reg_on)

           {

                     result = ((1 << NT3H2X11_NC_REG_PTHRU_ON_OFF_SHIFT) & NT3H2X11_NC_REG_PTHRU_ON_OFF_M);

           }

           else

           {

                     result = ((0 << NT3H2X11_NC_REG_PTHRU_ON_OFF_SHIFT) & NT3H2X11_NC_REG_PTHRU_ON_OFF_M);

           }

           write_data[0] = NT3H2X11_I2C_SESSION_REGS_MEM_ADDR;

           write_data[1] = NTAG_MEM_OFFSET_NC_REG; // reg index

           write_data[2] = NTAG_NC_REG_MASK_PTHRU_ON_OFF; // reg mask

           write_data[3] = result; // ns reg index

           ret = nt3h2x1->i2c->write(nt3h2x1->i2c, NT3H_SLAVE_ADDRESS, write_data, 4);

}

PATH-THROUGH operation 100% on normal case

Regards.