NHS3100 OpenOCD support

[jean-christiand]

Hello,

I like to add the MHS3100 support to OpenOCD. OpenOCD already support a lot of NXP LPCxxxx devices and I wonder if the NHS3100 architecture is close enough to one of already existing LPCXXX architecture to simply modify existing OpenOCD source files. In particular, it look like OpenOCD manage all LPCXXXX internal flash programming into a single lpc2000.c code that actually know the following flash programming variants:

lpc2000_v1,
lpc2000_v2,
lpc1700,
lpc4300,
lpc800,
lpc1100,
lpc1500,
lpc54100,

Does on of them fit the NHS3100 flash programming variant ?

Best Regards.

[driesmoors]

Hi,

We don't support OpenOCD in combination with the NHS31xx ICs.

You will need to create your own cfg file.

That said, we once have looked into it. You can find below the configuration script we made. THIS IS UNTESTED. THIS WILL LIKELY NOT WORK. And, we cannot support you with this. Use it as a starting point, and of course, do share you results ;-)

adapter_khz 1000
swj_newdap NHS3100 cpu -irlen 4 -expected-id 0
target create NHS3100.cpu cortex_m -endian little -chain-position NHS3100.cpu
NHS3100.cpu configure -work-area-phys 0x10000000 -work-area-size 0x2000 -work-area-backup 0
flash bank NHS3100.flash lpc2000 0x0 0x7800 0 0 NHS3100.cpu nhs3100 500 0

NHS3100.cpu configure -event reset-assert-pre {
mww 0x40048024 0
mdw 0x40048020
mem2array temp 32 0x40048020 1
set temp(0) [expr $temp(0) & 0xFFFFFFF0]
set temp(0) [expr $temp(0) | 0x08]
array2mem temp 32 0x40048020 1
mdw 0x40048020
mww 0x40048024 0
mww 0x40048024 1
}

NHS3100.cpu configure -event gdb-attach {
halt
}

[tomasvanek]

Hi Dries,

I'm a developer from OpenOCD team. We are about to merge the change Jean contributed.

I'm very unsure about setting the CPU clock just before reset. Can you please explain why it is necessary?

Thanks

   Tomas

[driesmoors]

Hello Tomas,

Thank you for reaching out. I'll take this discussion offline.
BR, Dries.

[jean-christiand]

Dear Dries, I really appreciate your attention on this subject, but I'm surprised by your last message. I do not know how I should understand it. I will still try to improve the patch with the information I can get.

[driesmoors]

No worries. The community forum didn't seem the right place to discuss this with Tomas, that's all. This integration task of his is not about a problem customers will face as well. I'll make sure you'll be in the loop as well.

[jean-christiand]

Hello Dries,

Many thanks for your very helpful response. I reworked a bit the configuration (see below) and it worked with the addition to this lpc2000.c patch Gerrit Code Review  to avoid the message 'BUG: unknown bank->size encountered'.

adapter_khz 10
swd newdap NHS3100 cpu -irlen 4 -expected-id 0
dap create NHS3100.dap -chain-position NHS3100.cpu
target create NHS3100.cpu cortex_m -endian little -dap NHS3100.dap
NHS3100.cpu configure -work-area-phys 0x10000000 -work-area-size 0x2000 -work-area-backup 0
flash bank NHS3100.flash lpc2000 0x0 0x7800 0 0 NHS3100.cpu lpc800 500

NHS3100.cpu configure -event reset-assert-pre {
 mww 0x40048024 0
 mdw 0x40048020
 mem2array temp 32 0x40048020 1
 set temp(0) [expr $temp(0) & 0xFFFFFFF0]
 set temp(0) [expr $temp(0) | 0x08]
 array2mem temp 32 0x40048020 1
 mdw 0x40048020
 mww 0x40048024 0
 mww 0x40048024 1
}

NHS3100.cpu configure -event gdb-attach {
 halt
}

As I understand, the reset-assert-pre event procedure ensure to run the clock at 500kHz.

[jean-christiand · Accepted solution]

I have merged your proposal with my patch to OpenOCD: Add LPC8Nxx and NHS3xx support. 

At least with the two probes I have tested (LPC-Link-2 with JLink firmware, and FT2232), the NHS3100 is sometime in a such state that it's not detected on the SWD bus. A low pulse on the chip RESETN signal solve the problem. Unfortunately OpenOCD is actually not able to generate a such pulse before the SWD init.

[driesmoors]

Thank you very much. When the IC is in Power-off or Deep Power down mode, the HW block is also unpowered. These modes can be entered by firmware. The default firmware image (flashe din production) makes use of this. Best is to avoid these power modes during development, and only later add them when the functionality is complete. For testing the NHS31xx ICs in combination with OpenOCD, I would advise to flash the IC with the blinky demo app beforehand.

[jean-christiand]

Thanks Dries for your message.

From my experience with the NHS3100, SWD probe failure can happen even without Power Off or Deep Power Down mode. A RESETN pulse always make the SWD probe happy. Good enough to reliably program the NHS3100 with OpenOCD (more reliable than the LPCExpresso).

I use a hacked configuration for openOCD that ensure a pulse is send to RESETN before SWD probing. It only work with FTDI adapter. This example use ADBUS7 as RESETN signal:

ftdi_layout_init 0x0000 0x00fb
ftdi_layout_signal nSRST -ndata 0x0080
reset_config srst_only srst_nogate connect_assert_srst

The trick is to init the FTDI IO with RESETN low and to make OpenOCD think it must assert the SRTS by in fact pull the RESETN signal high. With this, OpenOCD manage the RESETN signal the wrong way, because the logical level is inverted. But since OpenOCD don't need the SRTS signal for normal operation, this have no bad consequences, at least to just program the flash.