CLRC663 Plus: Issue with floating TVDD ?

[Krill]

Hello,

I am using a regulator to provide 4.1V to TVDD. The regulator can be switched on and off depending on use case. When the regulator is turned off, the TVDD node becomes high impedance, hence the potential is slowly discharged. The PDOWN pin is pulled high when regulator is turned off.

I have seen a strange behaviour on the TX side, which correlates to the discharge of the regulator on the TVDD node. 

Is it ok to supply TVDD the way I have described? I did not expect anything to happen on the TX side while CLRC is powered down by PDOWN pin.

Thanks

Sebastian

[Fabian_R]

Hello sir,

This is NXP's customer support. Would you mind letting me know if you are using a custom board? We don't have any information regarding this phenomenon.

Would you mind sharing a session when this occurs. Is possible that there is a relation of the Regulator is turning off and, TVDD impedance. Is better if I consult this to the experts by showing a session when this happens.

Is recommended in section 8.9.1 of CLRC663 Datasheet is recommended to block capacitance with 2 capacitors, 100 nF parallel to 1.0 μF.