Odd data transfers with FLEXIO_SPI slave

[Henrik-Wires]

I am trying to get tje the MBDT example s32k3xx_spi_async_interr_s32ct to work on s32k396_bga_dc1 + MB, using lpspi2 (master) + flexio_spi_0 (slave), but I am getting very odd results.

lpspi2 is configured for async mode with external buffer. No DMA.

flexio_spi_0 is configured for IB usage in async mode with DMA.

Trying to mimic the SPI configuration of the default K344 profile combined with S32 DS example Spi_Transfer_S32K396.

lpspi2 works fine. If I loop sout to sin then the exact same value is looped back like expected.

But the flexio_spi_0 in slave mode behaves very and only updates randomly. Both input and output behaves odd. Between updates it keeps repeating the same value until it updates suddenly. And from time to time it even behaves well. I can not find any consistent pattern in what it is doing and is out of ideas what might cause this kind of behavior.

The same configuration works just fine with the S32DS example Spi_Transfer_S32K396 after correcting the LPSPI2 pinout and adjusting the buffer size to match.

The callbacks on I/O completetion is called like a clockwork on both. But the data to/from flexio_spi_0 does not behave well when run periodic transferring only 1 byte.

Have attached the mex file I am using. 

The board is wired like

Channel	CLK	DI	DO	CS
LPSPI2	P23-15	P23-13	P27-8	P23-9
FLEXIO_SPI_0	P13-7	P18-12	P10-8	P17-4

P23-15 <-> P13-7
P23-13 <-> P10-8
P27-8 <-> P18-12
P23-9 <-> P17-4

If I adjust the model priorities so that the slave transfer is triggered before the master transfer then it works somewhat better, but far from reliable.

End goal is to have an automatic periodic repeating master transaction on flexio_spi collecting measurements from a clocked serial device. Each transfer is less than 13 bit so shouldn't even really need any buffers at all other than what is provided by flexio hardware module. But first goal is to understand and get data flowing reliably.