K70F150M MQX 4.2 example project for clock configs ?

[nitinharish]

I am using MQX 4.2.0.2 with IAR EWARM.

I have got K70f120M tower kit and example project running without any issue.

Now, I want to create a project for K70F150M processor, how do I even start, which files need to be changed from K70F120M to get to K70F150M.

Has anyone done this before, or can any one point me to the files that need to be changed. MQX 4.2.0.2 has no example to do so.

To me it sounds like bsp_cm.h needs to have a correct clock frequency and then user_config.h needs to have correct MQX_CPU define.

Is that all ?

Can anyone guide me mjbcswitzerland‌, DavidS‌, soledad, MeganHansen, RadekS, macl

Thanks in advance.

Nitin

[soledad]

Hello,

You need to follow the bellow steps:

1. Please check the bsp_cm.c file located at the path: C:\Freescale\Freescale_MQX_4_2\mqx\source\bsp\name_board
2. Localize the void _bsp_initialize_hardware(void) function
3. Modify this function according your needs.

In addition please check the “How-to Change Default Clock Settings in Kinetis BSPs” document attached to this thread.

Have a great day,
Sol

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[nitinharish]

It sounds like MQX 4.2.0.2 half heartedly supports MK70FX512VMJ150 device, because once I changed MQX_CPU from PSP_CPU_MK70F120M to PSP_CPU_MK70F150M, BSP does not even find "MK70F15.h" from kinetis.h, luckily, I had processor expert so copied the file manually to "\mqx\source\psp\cortex_m\cpu"

And now, I have a problem compiling BSP because in fsl_flexcan_driver.c is only defining bit_rate_table for PSP_CPU_MK70F120M,  PSP_CPU_MK65F180M, PSP_CPU_MK60DN512Z and  PSP_MQX_CPU_IS_VYBRID.

I am NOT sure if I add PSP_CPU_MK70F150M to the group PSP_CPU_MK70F120M, it is fine or NOT ?

Here is the current table (in fsl_flexcan_driver.c):

//! The following table is based on the assumption that BSP_CANPE_CLOCK is defined. The CAN bit
//! timing parameters are calculated by using the method outlined in AN1798, section 4.1.
//! A maximum time for PROP_SEG will be used, the remaining TQ will be split equally between PSEG1
//! and PSEG2, if PSEG2 >=2.
//! RJW is set to the minimum of 4 or PSEG1.
//! The table contains bit_rate (Hz), propseg, pseg1, pseg2, pre_divider, and rjw.
#if (MQX_CPU == PSP_CPU_MK70F120M) || (MQX_CPU == PSP_CPU_MK65F180M)
const flexcan_bitrate_table_t bit_rate_table[] = {
 { 125000, 6, 7, 7, 19, 3}, /* 125 kHz */
 { 250000, 6, 7, 7, 9, 3}, /* 250 kHz */
 { 500000, 6, 7, 7, 4, 3}, /* 500 kHz */
 { 750000, 6, 5, 5, 3, 3}, /* 750 kHz */
 {1000000, 6, 5, 5, 2, 3}, /* 1 MHz */
};
#elif (MQX_CPU == PSP_CPU_MK60DN512Z)
const flexcan_bitrate_table_t bit_rate_table[] = {
 { 125000, 6, 7, 7, 15, 3}, /* 125 kHz */
 { 250000, 6, 7, 7, 7, 3}, /* 250 kHz */
 { 500000, 6, 7, 7, 3, 3}, /* 500 kHz */
 { 750000, 6, 3, 3, 3, 3}, /* 750 kHz */
 {1000000, 6, 7, 7, 1, 3}, /* 1 MHz */
};
#elif PSP_MQX_CPU_IS_VYBRID
const flexcan_bitrate_table_t bit_rate_table[] = {
 { 125000, 6, 7, 7, 21, 3}, /* 125 kHz on 66 MHz IPG*/
 { 250000, 6, 7, 7, 10, 2}, /* 250 kHz */
 { 500000, 6, 6, 6, 5, 3}, /* 500 kHz */
 {1000000, 3, 2, 2, 5, 1}, /* 1 MHz */
};
#endif

Let me know, if I am on the wrong track here ?

Thanks

[nitinharish]

I went ahead and made the code change in fsl_flexcan_driver.c as following:

//! The following table is based on the assumption that BSP_CANPE_CLOCK is defined. The CAN bit
//! timing parameters are calculated by using the method outlined in AN1798, section 4.1.
//! A maximum time for PROP_SEG will be used, the remaining TQ will be split equally between PSEG1
//! and PSEG2, if PSEG2 >=2.
//! RJW is set to the minimum of 4 or PSEG1.
//! The table contains bit_rate (Hz), propseg, pseg1, pseg2, pre_divider, and rjw.
#if (MQX_CPU == PSP_CPU_MK70F120M) || (MQX_CPU == PSP_CPU_MK65F180M) || (MQX_CPU == PSP_CPU_MK70F150M)
const flexcan_bitrate_table_t bit_rate_table[] = {
{ 125000, 6, 7, 7, 19, 3}, /* 125 kHz */
{ 250000, 6, 7, 7, 9, 3}, /* 250 kHz */
{ 500000, 6, 7, 7, 4, 3}, /* 500 kHz */
{ 750000, 6, 5, 5, 3, 3}, /* 750 kHz */
{1000000, 6, 5, 5, 2, 3}, /* 1 MHz */
};
#elif (MQX_CPU == PSP_CPU_MK60DN512Z)
const flexcan_bitrate_table_t bit_rate_table[] = {
{ 125000, 6, 7, 7, 15, 3}, /* 125 kHz */
{ 250000, 6, 7, 7, 7, 3}, /* 250 kHz */
{ 500000, 6, 7, 7, 3, 3}, /* 500 kHz */
{ 750000, 6, 3, 3, 3, 3}, /* 750 kHz */
{1000000, 6, 7, 7, 1, 3}, /* 1 MHz */
};
#elif PSP_MQX_CPU_IS_VYBRID
const flexcan_bitrate_table_t bit_rate_table[] = {
{ 125000, 6, 7, 7, 21, 3}, /* 125 kHz on 66 MHz IPG*/
{ 250000, 6, 7, 7, 10, 2}, /* 250 kHz */
{ 500000, 6, 6, 6, 5, 3}, /* 500 kHz */
{1000000, 3, 2, 2, 5, 1}, /* 1 MHz */
};
#endif

But now, I am facing a very weird issue:

When I try to run MQX example "nandflash_demo.c", it works fine on the tower kit TWR-K70 with TWR-SER card attached to it. but if I remove TWR-SER card from my tower, the code just stalls inside "bsp_cm.c", at the following highlighted location:

void __pe_initialize_hardware(void)
{
_bsp_watchdog_disable();

#if MQX_ENABLE_LOW_POWER
/* Reset from LLWU wake up source */
if (_lpm_get_reset_source() == MQX_RESET_SOURCE_LLWU)
{
PMC_REGSC |= PMC_REGSC_ACKISO_MASK;
}
#endif
/*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/

/*** ### MK70FN1M0VMJ12 "Cpu" init code ... ***/
/*** PE initialization code after reset ***/
/* SIM_SCGC6: RTC=1 */
SIM_SCGC6 |= (uint32_t)0x20000000UL;
if ((RTC_CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the OSCILLATOR is not already enabled */
/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
RTC_CR &= (uint32_t)~0x3C00UL;
/* RTC_CR: OSCE=1 */
RTC_CR |= (uint32_t)0x0100UL;
/* RTC_CR: CLKO=0 */
RTC_CR &= (uint32_t)~0x0200UL;
}

/* System clock initialization */
/* SIM_SCGC5: PORTE=1,PORTC=1,PORTA=1 */
SIM_SCGC5 |= (uint32_t)0x2A00UL; /* Enable clock gate for ports to enable pin routing */
if ( *((uint8_t*) 0x03FFU) != 0xFFU) {
MCG_C3 = *((uint8_t*) 0x03FFU);
MCG_C4 = (MCG_C4 & 0xE0U) | ((*((uint8_t*) 0x03FEU)) & 0x1FU);
}
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=2,OUTDIV4=5,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = (uint32_t)0x01250000UL; /* Update system prescalers */
/* SIM_CLKDIV4: NFCDIV=7 */
SIM_CLKDIV4 |= SIM_CLKDIV4_NFCDIV(7);
/* SIM_SOPT2: PLLFLLSEL=1 */
SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~0x00020000UL) | (uint32_t)0x00010000UL); /* Select PLL 0 as a clock source for various peripherals */
/* SIM_SOPT1: OSC32KSEL=1 */
SIM_SOPT1 |= (uint32_t)0x00080000UL; /* RTC oscillator drives 32 kHz clock for various peripherals */
/* SIM_SCGC1: OSC1=1 */
SIM_SCGC1 |= (uint32_t)0x20UL;
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA_PCR18 &= (uint32_t)~0x01000700UL;
/* PORTE_PCR24: ISF=0,MUX=0 */
PORTE_PCR24 &= (uint32_t)~0x01000700UL;
/* PORTE_PCR25: ISF=0,MUX=0 */
PORTE_PCR25 &= (uint32_t)~0x01000700UL;
/* Switch to FBE Mode */
/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0_CR = (uint8_t)0x80U;
/* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC1_CR = (uint8_t)0x80U;
/* MCG_C7: OSCSEL=0 */
MCG_C7 &= (uint8_t)~(uint8_t)0x01U;
/* MCG_C10: LOCRE2=0,??=0,RANGE1=2,HGO1=1,EREFS1=1,??=0,??=0 */
MCG_C10 = (uint8_t)0x2CU;
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=1 */
MCG_C2 = (uint8_t)0x21U;
/* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
MCG_C1 = (uint8_t)0xA8U;
/* MCG_C4: DMX32=0,DRST_DRS=0 */
MCG_C4 &= (uint8_t)~(uint8_t)0xE0U;
/* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=4 */
MCG_C5 = (uint8_t)0x04U;
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=8 */
MCG_C6 = (uint8_t)0x08U;
/* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=3 */
MCG_C11 = (uint8_t)0x03U;
/* MCG_C11: PLLCLKEN1=1 */
MCG_C11 |= (uint8_t)0x40U; /* Enable the PLL */
/* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=8 */
MCG_C12 = (uint8_t)0x08U;
while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to PBE Mode */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=8 */
MCG_C6 = (uint8_t)0x48U;
while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL locked */
}
/* Switch to PEE Mode */
/* MCG_C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
MCG_C1 = (uint8_t)0x28U;
while((MCG_S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
}
/* MCG_C6: CME0=1 */
MCG_C6 |= (uint8_t)0x20U; /* Enable the clock monitor */
/*** End of PE initialization code after reset ***/

/*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/

}

Is TWR-SER supplying some clock/oscillator input to TWR-K70 ? mjbcswitzerland‌DavidS‌ soledad macl ?

[nitinharish]

Never mind, I figured out that Jumper J18 on Rev C TWR-K70 board if connected feeds 50MHz clock input to MCU from TWR-SER card, if J18 is OPEN, onboard 50MHz clock feeds the MCU.

[mjbcswitzerland]

Nitin

In the uTasker project I change

#define KINETIS_MAX_SPEED    120000000
to
#define KINETIS_MAX_SPEED    150000000

to move from K70F120 to K70F150.

The only effect is to allow faster DDR, Bus and core speeds but it still runs at 120MHz unless I also change the PLL clock multiplier to 1.25x higher.

Therefore I conclude that you should be able to use the exact same example project and just increase the multiplier (if anything complains, just comment out the checks). If you want to make a project explicitly for this you may have to copy a lot of files and adjust a couple of lines in some headers (I experimented doing this in KSDK once and it required 50MBytes of new files in order to achieve a couple of lines of code change for a specific processor and took hours.....).

Regards

Mark