How can I use the Watchdog functionality in MQX?

[OOLife]

Hello, everyone,

CPU: MCF52259

Tool: CW 7.2

OS: MQX 3.4

I want to error recovery using watchdog functionality.

I've tested example located in mqx folder.

(C:\Program Files\Freescale\Freescale MQX 3.4\mqx\examples\watchdog)

1. Call other function in Watchdog handler function

handle_watchdog_expiry() function is working and seems good.

However, some function is not working correctly in this function for example TCP/IP send function.

Is it correct?

2. Detecting watchdog status when boot up

I just want to RESET using RCR register when watchdog expired.

Then, how can I detect when I boot up, it is watchdog reset or normal reset?

3. Normal Watchdog strategy in MQX on MCF52259

Is there any example or article about watchdog usage on MQX?

Thank you for reading this.

Best Regards

O.O Life.

[DavidS]

Hi O. O Life,

The examples/watchdog is actually setting up a task software watchdog timer.  This timer is using the BSP tick timer (PIT0) to test whether the task watchdog has expired and not using the on-chip core watchdog module.

The on-chip core watchdog is partially setup in the init_bsp.c file.   

Several things need to be added to make the core watchdog operate:

1) create a core watchdog ISR that can implement the software reset operation (RCR register bit 7).

2) initialize the ICR for core watchdog and clear the IMRL bit for the software watchdog (bit 8).

3) register/install the ISR (_int_install_isr())

Hassles:

- once core watchdog is running, system is hard to debug and the timer does not stop when debugger halts processor.

Read RSR register (in Reset Controller Module right after the RCR definition) to check what caused the reset.  My code is not doing that.

I've attached my enhanced version of the example/watchdog source code file that sets everything up.  I'm running from internal flash and you can monitor the serial port to see the value of "n" being printed.  If you wait ~10 seconds the task handle_watchdog_expiry() function gets called.

If you halt in that function on the ___mqx_exit(1); function call, then the core watchdog will time out quickly and once you resume running the system will have reset.

Note that I lowered the core watchdog timeout value in init_bsp.c _bsp_setup_watchdog() as follows:

| MCF5225_SCM_CWCR_CWT(BSP_WATCHDOG_DELAY-2); //DES added -2 to speed testing
Otherwise you would have to halt the debugger and wait about a minute to get the core watchdog to timeout.

Regards,

David

[davidaustinsorr]

Hi guys,

you are talking about an attached source code... where can I find it?

Thanks,

Dave

[OOLife]

Hi DavidS..

Thank you so much about answer my question and sharing your code.

I've tested my code according to your comment.

But, my code is not working.

When I boot up, I read the RSR register.

RSR Register value

    Power On ==> 0x48 It's good.

    Soft Reset ==> 0x20   It also good.

    Watchdog Reset ==> 0x20 different from my expectation. (actually, my expectation value is 0x10 or 0x80)

My application already use Soft Reset(RCR=0x80) functionality, so I want to know there is watchdog reset or not.

But, I don't catch the watchdog reset condition by reading RSR register...

How can I reset my system with the SET bit BWT or WDR in RSR register.

Could you comment about this?

or, could you show me the reading RSR register reading example?

Anyway, Thank you very much.

Regards..

O.O Life

[DavidS · Accepted solution]

Hi O.O Life,

To test I placed a breakpoint in the task watchdog handle_watchdog_expiry() function after the printf call.

If my core watchdog was setup to expire quickly then just hitting the breakpoint and stepping or resuming execution would show that the core watchdog generated a reset. Alternatively you can set breakpoint in _bsp_core_wd_isr() interrupt, run the code, break/halt and wait for longer than what the core watchdog timeout is and then resume execution to see if core watchdog interrupt breakpoint gets hit.  If yes then use the "View-->Register" pull-down to inspect the RSR bits.

The RSR bits BWT and WDR are for the backup watchdog timer and not the core timer example I'm showing you.  So those bits should not be setting.

NOTE: RSR register is read-only.

When the SOFT bit sets, that implies that the core watchdog interrupt fired properly as it is its code that issues the Soft Reset by setting the setting the SOFTRST bit in the RCR register.

I re-ran my code that outputs the RSR register value and it shows External Reset (0x04) then after the task watchdog expires and my debugger hits breakpoint and I wait until the core watchdog times out, I resume execution and the RSR now is Soft (0x20).

Here is how to read the RSR:

VMCF5225_STRUCT_PTR reg_ptr = _PSP_GET_IPSBAR();
printf("\n %d     RSR: 0x%P", n, reg_ptr->CCM.RSR);

Regards,

David

[OOLife]

Hi DavidS..

I really appreciate your reply.

When system boot up, I can distinguish RESET type.

Thanks.

Best Regards.

O.O Life