FlexCan RxFIFO

[derekkrouze]

Hello,

I am currently trying to use the FlexCan RxFifo on a K61 using MQX 4.1.1. However I am noticing that the messages always come in on the last buffer while mqx always checks message buffer 0. So when I start the system the first 5 messages my CAN system receives are all 0's and my system is always 5 messages behind. Am I missing initializing something so they system doesn't assume that all the FIFO buffers are in use already? I see in the datasheet that "Before enabling the RFEN, the CPU must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now belonging to FIFO as having contents to be serviced" however I look at the reigsters and it appears everything is cleared correctly. Any help would be greatly appreciated.

Thanks

-Derek

[lisamichauxsmit]

In case any one else is looking at this thread, I want to make sure they realize what was happening here.

The fsl_flexcan driver in MQX 4.1 has a bug: the interrupt happens when the message comes in, but it doesn't copy out the message before it clears the interrupt.  When the driver reads out the message later, it always seems like you're queue-length messages behind.

This has been fixed in Kinetis SDK 1.1.0, but I don't know how that applies to the straight MQX distributions.

[arnogir]

Hello

This bug seems always be present in MQX 4.2.

Are they a workaround or a patch to apply?

[soledad]

Hi Derek,

Are you using the MQX drivers?

Could you please try using the flexcan example? This is located at the path: C:\Freescale\Freescale_MQX_4_1\mqx\examples\can\flexcan

Have a great day,
Sol

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[derekkrouze]

Thanks for the response soledad,

I am using the MQX drivers and have looked through the example code given, unfortunately the example doesn't seem geared towards the RxFIFO and I seem to be doing everything they are in the example. It feels like the hardware thinks message buffers 0-5 are in use when the first message comes in. I have stepped through the code and when the interrupt is fired my message is in the RxFIFO buffer 0 and then when the interrupt is cleared it goes to the end of the fifo and the system reads packets of zeros. After 6 messages are received I finally get my very first message to be processed.

-Derek