External SPI Chip select

[Mohsin455]

Hi All,

             I am using K60N5112 on my custom board  with MQX3.8. I need to know more information on the SPI chip select (CS)

1) On my custom board I am using SPI1 with the following chips selects

SPI1_PCS1 (PTB9)

SPI1_PCS0 (PTB10)

External_CS_1 (PTB7)

External_CS_2 (PTB8)

SPI1_SCK (PTB11)

SPI1_SOUT (PTB16)

SPI1_SIN (PTB17)

Is it possible to use external chip selects with MQX3.8 and K60N512 ?

2) How do we select which ship select we want to use (suppose we first want to send data on device 1 using SPI1_PCS0 and then send data on device 2 using SPI1_PCS1) ?

Thanks,

Mohsin

[PetrM]

Hello,

please take a look at main BSP header file of some coldfire 51xx and the MQX SPI example itself.

You need to add some more defines to your K60 BSP to make GPIO chip selects working:

#define BSP_SPI1_GPIO_CS1                   (GPIO_PORT_B | GPIO_PIN7)
#define BSP_SPI1_GPIO_CS2                   (GPIO_PORT_B | GPIO_PIN8)
#define BSP_SPI_MUX_GPIO                     (LWGPIO_MUX_B7_GPIO)

#define BSP_SPI_MEMORY_GPIO_CS    (BSP_SPI1_GPIO_CS1)
#define BSP_SPI_MEMORY_SPI_CS        (SPI_PUSHR_PCS(1 << 2))

As you can see, LWGPIO driver is used in CS callback to drive chip select on pin PTB7.

Your new CS is mapped to DSPI HW chip select 2.

You can switch between chip selects using ioctl call to IO_IOCTL_SPI_SET_CS:

chip_select = SPI_PUSHR_PCS(1 << 0);

ioctl (spi_fd, IO_IOCTL_SPI_SET_CS, &chip_select);

fwrite ();

fflush ();

...

chip_select = SPI_PUSHR_PCS(1 << 1);

ioctl (spi_fd, IO_IOCTL_SPI_SET_CS, &chip_select);

fwrite ();

fflush ();

...

chip_select = BSP_SPI_MEMORY_SPI_CS;

ioctl (spi_fd, IO_IOCTL_SPI_SET_CS, &chip_select);

fwrite ();

fflush ();

...

Regards,

PetrM

[Mohsin455]

Hi PetM,

                Thanks for the information. I need a bit more information as I am a bit confused. The internal chip select 0 and 1 are defined in init_gpio.c and the external chip select 2 and 3 are defined in twrl60n512.h. (please see below)

What else do I need ?

Also I could not understand the following from your earlier post " As you can see, LWGPIO driver is used in CS callback to drive chip select on pin PTB7.

Your new CS is mapped to DSPI HW chip select 2."  Is this right in your example ?

/////////////////////////////////////////////////////////////////////////////
// Within twrl60n512.h
/////////////////////////////////////////////////////////////////////////////

/*-----------------------------------------------------------------------------
**                      DSPI
*/

#define BSP_DSPI_RX_BUFFER_SIZE          (32)
#define BSP_DSPI_TX_BUFFER_SIZE          (32)
#define BSP_DSPI_BAUDRATE                (1000000)
#define BSP_DSPI_INT_LEVEL               (4)
#define BSP_SPI_MEMORY_CHANNEL           2

#define BSP_SPI1_GPIO_CS2                (GPIO_PORT_B | GPIO_PIN7)
#define BSP_SPI1_CS2_MUX_GPIO            (LWGPIO_MUX_B7_GPIO)

#define BSP_SPI1_GPIO_CS3                (GPIO_PORT_B | GPIO_PIN8)
#define BSP_SPI1_CS3_MUX_GPIO            (LWGPIO_MUX_B8_GPIO)


/////////////////////////////////////////////////////////////////////////////
// Within init_gpio.c
/////////////////////////////////////////////////////////////////////////////
        case 1:
            /* Configure GPIOB for DSPI1 peripheral function     */
            pctl = (PORT_MemMapPtr)PORTB_BASE_PTR;

            pctl->PCR[9]  = PORT_PCR_MUX(2);     /* DSPI1.PCS1   */
            pctl->PCR[10] = PORT_PCR_MUX(2);     /* DSPI1.PCS0   */
            pctl->PCR[11] = PORT_PCR_MUX(2);     /* DSPI1.SCK    */
            pctl->PCR[16] = PORT_PCR_MUX(2);     /* DSPI1.SOUT   */
            pctl->PCR[17] = PORT_PCR_MUX(2);     /* DSPI1.SIN    */

            /* Enable clock gate to DSPI1 module */
            sim->SCGC6 |= SIM_SCGC6_SPI1_MASK;
            break;

Thanks,

Mohsin

[PetrM · Accepted solution]

Hello,

sorry for confusion, I was addressing the MQX SPI example.
The GPIO for your external chip selects is setup and driven there.
Your changes are ok, now you have to add into your BSP some more defines required by the example.
Please check the example code to see how it works.

#define BSP_SPI_MUX_GPIO                    (BSP_SPI1_CS2_MUX_GPIO)
#define BSP_SPI_MEMORY_GPIO_CS    (BSP_SPI1_GPIO_CS2)
#define BSP_SPI_MEMORY_SPI_CS        (SPI_PUSHR_PCS(1 << 2))

So CS0 and CS1 will be handled by HW, for the CS2 the GPIO callback will be used.
You have to extend the example code for the CS3 accordingly.

Regards,
PetrM