Disable cache on K60F120

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Disable cache on K60F120

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dev25
Contributor II

Hello,

I am wondering if there is any cache feature in MQX for the Freescale tower K60F120M, and if so, how could I disable it ?

Any help would be grateful,

Best regards,

Camille

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DavidS
NXP Employee
NXP Employee

Hi Camille,

MQX setups the Instruction/Data 8Kbyte caches to default setting in BSP init_bsp.c file as follows:

    /** Cache settings **/

    /* Make sure that cache region settings has correct value(reset value).

    This value allow maximal perfomance settings for cache regions because of some regions are:

    non-cacheable ,non-cacheable and Write-through or non-cacheable and Write-throug or only Write_back*/

    LMEM_PSCRMR = 0xAA0FA000u;

    LMEM_PCCRMR = 0xAA0FA000u;

    /*folowed 2 functions enable caches (instruction and data cache) and invalidate caches*/

    _DCACHE_ENABLE(0);

    _ICACHE_ENABLE(0);

You can change the _DCACHE_ENABLE(0); to _DCACHE_DISABLE(0); .

You can change the _ICACHE_ENABLE(0); to _ICACHE_DISABLE(0); .

The respective macros are defined in kinetis.h header.

Regards,

David

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936件の閲覧回数
DavidS
NXP Employee
NXP Employee

Hi Camille,

MQX setups the Instruction/Data 8Kbyte caches to default setting in BSP init_bsp.c file as follows:

    /** Cache settings **/

    /* Make sure that cache region settings has correct value(reset value).

    This value allow maximal perfomance settings for cache regions because of some regions are:

    non-cacheable ,non-cacheable and Write-through or non-cacheable and Write-throug or only Write_back*/

    LMEM_PSCRMR = 0xAA0FA000u;

    LMEM_PCCRMR = 0xAA0FA000u;

    /*folowed 2 functions enable caches (instruction and data cache) and invalidate caches*/

    _DCACHE_ENABLE(0);

    _ICACHE_ENABLE(0);

You can change the _DCACHE_ENABLE(0); to _DCACHE_DISABLE(0); .

You can change the _ICACHE_ENABLE(0); to _ICACHE_DISABLE(0); .

The respective macros are defined in kinetis.h header.

Regards,

David

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