I'm working on a project using MQX lite and KL15, I've been stuck in a hard fault for several days now...
I've obtained the following code to extract the PC from the stack and figure-out what is causing the hard fault (thank you Freescale):
__attribute__((naked))
PE_ISR(Cpu_ivINT_Hard_Fault)
{
__asm volatile (
" movs r0,#4 \n"
" movs r1, lr \n"
" tst r0, r1 \n"
" beq _MSP \n"
" mrs r0, psp \n"
" b _HALT \n"
"_MSP: \n"
" mrs r0, msp \n"
"_HALT: \n"
" ldr r1,[r0,#20] \n"
" bkpt #0 \n"
);
}
But saw the following code in an other forum (Cortex-M3: Tips/Tricks to debug a Hard Fault?)
The Cortex-M pushes 8 registers on the stack on Hard Fault exception. Here is a code to read the memory address that caused it:
MRS R0,PSP ; Read PSP LDR R1,[R0,#24] ; Read Saved PC from Stack
In either case, both the #20 and the #24 offset returns 0x0 to R1 (supposed to be the PC that generated the hard fault)... A PC of 0x0 is either wrong or my code (along with MQX) has gone off on to the weeds big time.
I suppose the SP offset may be a different value but I have looked around the SP vicinity and have found a few probable code addresses related to MQX code blocks (Stack LIFO and 32 bit registers are easy to follow)... thus I suspect a problem with my MQX lite configuration... but I do not think I have messed with the MQX lite configuration outside of what Processor Expert allows me to... so could it be that Processor Expert has some potential MQX Lite kill switches available that it shouldn't have open to newbies like me?
I'm using serial port interrupts, 9600 bauds, I beak on the string composing routine and looks fine, I dunno if the serial port ISR is conflicting with OS Interrupts... But I have messed with priorities from 0 to 3 and all fail...
Any assistance will be much appreciated.
Kindest Reagards,
Carlos
