Clock switching issue in K70

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Clock switching issue in K70

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pramodk_g_
Contributor III

HI everyone,

                    I am using TWR K70 , MQX 4.0 and CW 10.5. In my project i want to run the processor at 3 different clock configuration,  like 120Mhz (active mode) 24Mhz (idle mode) and 2 Mhz sleep mode. In order to reduce the power conception i am generating 24Mhz from external 12Mhz oscillator ( so that i can disable 50 Mhz oscillator in future ) . For that i have created new clock configuration from existing pee configuration(Cpu_SetMCGModePEE) in bsp and it is working. But my issue is after switching few times  between these mode code gets hang in bsp. It is seems lie that code is waiting on the pll locking while loop in psp. I have attached my code below, please review and let me know were am went wrong.

For 120MHz and 2 MHz clocks i am using bsp clock configuration 0 and 2.

static void Cpu_SetMCGModePEE_12(uint8_t CLKMode)

{

  switch (CLKMode) {

    case 0U:

               

      /* Switch to PEE Mode */

      /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */

      OSC0_CR = (uint8_t)0x80U;                            

      /* MCG_C10: LOCRE2=0,??=0,RANGE1=2,HGO1=1,EREFS1=1,??=0,??=0 */

      MCG_C10 = (uint8_t)0x2CU;                            

      /* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */

      OSC1_CR = (uint8_t)0x80U;                            

      /* MCG_C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */

      MCG_C1 = (uint8_t)0x28U;                            

      /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=1 */

      MCG_C2 = (uint8_t)0x21U;                            

      /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=4 */

      MCG_C11 = (uint8_t)0x04U;                            

      /* MCG_C11: PLLCLKEN1=1 */

      MCG_C11 |= (uint8_t)0x40U;       /* Enable the PLL */

      /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=8 */

      MCG_C12 = (uint8_t)0x08U;                            

      /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=4 */

      MCG_C5 = (uint8_t)0x80U; 

      MCG_C5 |= (uint8_t)0x40U; 

      /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=8 */

      MCG_C6 = (uint8_t)0x44U;                            

      while((MCG_S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */

      }

      break;

    default:

      break;

  }

}

static void Cpu_SetMCGModePBE_12(uint8_t CLKMode)

{

  switch (CLKMode) {

    case 0U:

      /* Switch to PBE Mode */

      /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */

      OSC0_CR = (uint8_t)0x80U;                            

      /* MCG_C10: LOCRE2=0,??=0,RANGE1=2,HGO1=1,EREFS1=1,??=0,??=0 */

      MCG_C10 = (uint8_t)0x2CU;                            

      /* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */

      OSC1_CR = (uint8_t)0x80U;                            

      /* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */

      MCG_C1 = (uint8_t)0xA8U;                            

      /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=1 */

      MCG_C2 = (uint8_t)0x21U;                            

      /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=4 */

      MCG_C5 = (uint8_t)0x80U;     

       /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=1,??=0,??=0,PRDIV0=4 */

      MCG_C5 |= (uint8_t)0x40U;                            

      /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=8 */

      MCG_C6 = (uint8_t)0x44U;                            

      /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=4 */

      MCG_C11 = (uint8_t)0x04U;                            

      /* MCG_C11: PLLCLKEN1=1 */

      MCG_C11 |= (uint8_t)0x40U;       /* Enable the PLL */

      /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=8 */

      MCG_C12 = (uint8_t)0x08U;                            

      while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */

      }

      while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL locked */

      }

      break;

    case 1U:

      /* Switch to PBE Mode */

      /* OSC0_CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */

      OSC0_CR = (uint8_t)0x00U;                            

      /* MCG_C10: LOCRE2=0,??=0,RANGE1=2,HGO1=1,EREFS1=1,??=0,??=0 */

      MCG_C10 = (uint8_t)0x2CU;                            

      /* OSC1_CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */

      OSC1_CR = (uint8_t)0x00U;                            

      /* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */

      MCG_C1 = (uint8_t)0xAAU;                            

      /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=1 */

      MCG_C2 = (uint8_t)0x21U;                            

      /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=4 */

      MCG_C5 = (uint8_t)0x80U;     

      /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=1,??=0,??=0,PRDIV0=4 */

//      MCG_C5 |= (uint8_t)0x40U; 

      /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */

      MCG_C6 = (uint8_t)0x40U;                            

      /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=4 */

      MCG_C11 = (uint8_t)0x04U;                            

      /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */

      MCG_C12 = (uint8_t)0x00U;                            

      while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */

      }

      while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL locked */

      }

      break;

    default:

      break;

  }

}

Thanks,

Pramod.

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61 Views
RadekS
NXP Employee
NXP Employee

Please open function Cpu_SetMCGModePBE function in bsp_cm.c file and replace line MCG_C6 = (uint8_t)0x40U; by line MCG_C6 = (uint8_t)0x48U;    (it is inside case 1U:)

This will fix issue with “cannot change Clock source to 2MHz after 3 times.”

It is known issue and it will be fixed in next MQX release.


Best Regards,
RadekS

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