Hello,
I guess it's because of the clock configuration，help me find the reason
Yes, it is due to clock init in your SW.
Even if you set the clocks you need successful mode transition in ME module to complete in order changes to take effect.
Do the mode transition after clocks are configured:
Have a look at my reference example:
https://community.nxp.com/docs/DOC-330326
Best regards,
Peter
void Sys_Init(void)
{
//Enable external oscilator
MC_ME.DRUN_MC.B.XOSCON = 1;
// Set PLL0 to 200MHz
PLLDIG.PLL0CR.B.CLKCFG = 1; //Bypass mode PLL0 on
// RFDPHI1 = 10, RFDPHI = 2, PREDIV = 2, MFD = 14
PLLDIG.PLL0DV.R = 0x50000000 |0x00020000 |0x00002000 |0x0014 ; //predefined PLL0 divider register
// Set PPL0 as system clock
MC_ME.DRUN_MC.B.PLL0ON = 1; //Enable PLL0 for DRUN mode
MC_ME.DRUN_MC.B.SYSCLK = 0x2;
// System clock dividers //
// Enable system clock divider /4 -> 50MHz
// (PBRIDGE_0, PBRIDGE_1, SIPI, DMA_CH_MUX) - Use only odd DIV values(2,4,etc..)
// Enable divider | divide by 4
MC_CGM.SC_DC0.R = 0x80000000 | 0x30000;
// AUX_0 clock dividers //
MC_CGM.AC0_SC.B.SELCTL =0x2; //connect PLL0 to AXU_0
// MOTC_CLK clock devider = 3 -> 200MHz/2 = 100MHz
// Enable divider | divide by 2
MC_CGM.AC0_DC0.R = 0x80000000 | 0x10000;
// SGEN_CLK clock devider = 10 -> 200MHz/10 = 20MHz
// Enable divider | divide by 10
MC_CGM.AC0_DC1.R = 0x80000000 | 0xA0000;
// SAR ADC clock devider = 3 -> 200MHz/3 = 66.6MHz
// Enable divider | divide by 3
MC_CGM.AC0_DC2.R = 0x80000000 | 0x20000;
// AUX_1 clock dividers //
// FRAY_CLK clock devider = 5 -> 200MHz/5 = 40MHz
// Enable divider | divide by 5
MC_CGM.AC1_DC0.R = 0x80000000 | 0x40000;
// SENT_CLK clock devider = 3 -> 200MHz/3 = 66.6MHz
// Enable divider | divide by 3
MC_CGM.AC1_DC1.R = 0x80000000 | 0x20000;
// AUX_2 clock dividers //
// CAN_CLK clock devider = 5 -> 200MHz/5 = 40MHz
// Enable divider | divide by 5
MC_CGM.AC2_DC0.R = 0x80000000 | 0x40000;
// AUX_3 clock dividers //
// AUX Clock Selector 3 setup - source for PLL0 module
MC_CGM.AC3_SC.B.SELCTL =1; //connect (8..40MHz) XTALL to the PLL0 input
//0=IRC 1=XOSC
// AUX_4 clock dividers //
//AUX Clock Selector 4 setup - source for PLL1 module
MC_CGM.AC4_SC.B.SELCTL =3; //connect PLL0 to AUX4
// AUX_5 clock dividers //
MC_CGM.AC5_SC.B.SELCTL =0x2; //connect PLL0 to AXU_5
// LFAST PLL clock devider = 10 -> 200MHz/10 = 20MHz
// Enable divider | divide by 10
MC_CGM.AC5_DC0.R = 0x80000000 | 0x90000;
// AUX_6 clock dividers //
MC_CGM.AC6_SC.R = 0x02000000; //connect PPL0 to AUX_6
// CLKOUT_0 clock devider = 20 -> 200MHz/20 = 10MHz
// Enable divider | divide by 20
MC_CGM.AC6_DC0.R = 0x80000000 | 0x140000;
// AUX_10 clock dividers //
MC_CGM.AC10_SC.R = 0x02000000; //connect PPL0 to AUX_10
// ENET_CLK clock devider = 4 -> 200MHz/4 = 50MHz
// Enable divider | divide by 4
MC_CGM.AC10_DC0.R = 0x80000000 | 0x30000;
// AUX_11 clock dividers //
MC_CGM.AC11_SC.R = 0x02000000; //connect PPL0 to AUX_11
// ENET_TIME_CLK clock devider = 4 -> 200MHz/4 = 50MHz
// Enable divider | divide by 4
MC_CGM.AC11_DC0.R = 0x80000000 | 0x30000;
//Mode transition to apply the PLL0 setup and set Normal mode with PLL running
MC_ME.MCTL.R = 0x30005AF0; //DRUN Mode & Key
MC_ME.MCTL.R = 0x3000A50F; //DRUN Mode & Key
while(!MC_ME.GS.B.S_PLL0); //ME_GS Wait for PLL stabilization.
while(MC_ME.GS.B.S_MTRANS); //Waiting for end of transaction
while(MC_ME.GS.B.S_CURRENT_MODE != DRUN_MODE); // ME_GS Check DRUN mode has successfully been entered
MC_ME.DRUN_MC.B.PLL1ON = 1; //Enable PLL1 for DRUN mode
//Configure RunPeripheralConfiguration registers in ME_RUN_PC0
MC_ME.RUN_PC[0].B.DRUN = 1; //Enable DRUN mode for all peripherals using ME_RUN_PC[0]
// Set PLL1 to 200 MHz with 40MHz XOSC reference
PLLDIG.PLL1DV.R = 0x00020014; // MFD = 20, RFDPHI = 2
//Mode transition to apply the PLL0 setup and set Normal mode with PLL running
MC_ME.MCTL.R = 0x30005AF0; //DRUN Mode & Key
MC_ME.MCTL.R = 0x3000A50F; //DRUN Mode & Key
while(!MC_ME.GS.B.S_PLL0); //ME_GS Wait for PLL stabilization.
while(MC_ME.GS.B.S_MTRANS); //Waiting for end of transaction
while(MC_ME.GS.B.S_CURRENT_MODE != DRUN_MODE); // ME_GS Check DRUN mode has successfully been entered
}//Sys_Init
thank god！！！！thank you very much，it is work.
recently ,I even tried to use same block init code in boot and app project(The screenshot at the bottom is my code).I still dont know why the progress of programe is stuck here
It mean mode can not transition from drun to drun .Than I test set boot use RUN0 ,app use DRUN, that do not work also.
Does this mean that the two projects cannot use the same clock setting?
Best regards,
shaoduoduo
Thank for your reply.
before jump to app programe,I have closed the peripherals which has been opened ,and recovery them to the default values,clean ram and disable the interrupt.
I debug the project .
It seems that status bits in FCCU NCF,location at 0XFBF58080,is 0.
lastly,power source on board didnt changed.
Best regards
Shaoduoduo
Hello,
Ok. For reading faults of FCCU NCFSx registers you ahve to apply the procedure. Hope you are aware of that, otherwise you will always read 0 even if there are faults latched.
Best regards,
Peter
I located my mistakes.
when I use the same funtion of MC_MODE_INIT in boot and app programe,the mcu can not work.
If I mask this section in app programe, the program can jump smoothly.
At this time, the MCU is using PLL1 (200 MHz) as the system clock(setted in boot programe).if MCU Enable XOSC in DRUN mode and select as SYS_CLK in app programe ,core trigger error.
The solution is not to let MCU enter the DRUN mode with using XOSC as SYS_CLK , directly configure PLL clock, and then enter the DRUN mode after the pll clock have been configured .
Am I right？
Best regards.
