how to use S32R274 CAN mask

[zj_nuaa]

hallo, I need your help to set CAN mask for MCU S32R274.

i have a program for CAN receiving with interrupt.

 CAN_1.MB[0].CS.B.CODE = 0x0;           //MB inactive
 CAN_1.MB[0].CS.B.IDE = 0;
 CAN_1.MB[0].ID.R = 10;                                              //set standard ID
 CAN_1.MB[0].DATA.W[1] = 0x00000000;  //data1 set (optional)
 CAN_1.MB[0].DATA.W[0] = 0x00000000;  //data0 set (optional)
 CAN_1.MB[0].CS.B.CODE = 0x4;   //MB empty - ready for receive

If I set CAN receiving without MASK. I use IRMQ=0, RXMGMASK=0x00000000. it works as expected.
it can received MB0 no matter of the ID number.

But by setting following to enable MASK, it always failed. MASK does not work as it supposed to. 
try 1: IRMQ=0, RXMGMASK=0xFFFFFFFC. supposedly ID=10,11,12,13 should be received.
try 2: IRMQ=1, RXIMR0=0xFFFFFFFC.       supposedly ID=10,11,12,13 should be received.

Can you tell me how to set it up?

[alexandrunan]

Be aware the bits corresponding from standard ID from the mask are between 3 and 13 as MSB, second the RXMGMASK should be written only in freeze mode. so the mask should be RXMGMASK = 0x0FFC0000 and IRMQ=0

[bhtybyb]

Thanks for your apply. It's very help. And I have another question about RXMGMASK , how to set RXMGMASK  to special MB[i]?

[alexandrunan]

To set individual masking for a desired MB no you need to set IRMQ to 1 from MCR register this need to be done in freeze mode. If RxFIFO is disabled then is a 1 to 1 correspondence between  CAN_RXIMR and MB ID filter. If RxFIFO enable then watch on the description of RFFN bitfield from CTRL2 register of FlexCAN to see the correspondence between RXIMR and RXFGMASK registers and filters IDs. All this information is from Reference Manual. RM.