eqADC CFIFO triggering with HW and using eDMA to fill CFIFO

[0xEC]

hi everyone,

I am working with MPC5775E board, using PAL lib, and I am trying to control eqADC with eDMA and triggering eqADC with PIT. 

PIT generates interrupt and trigger eqADC properly, eDMA transfers command from system memory to CFIFO push register and also results are transferred from RFIFO to system memory by eDMA. 

My question is that should I explicitly start eDMA channel to fill CFIFO by calling EDMA_DRV_StartChannel() function. I want to make eDMA automatically start to fill CFIFO. By the way I do not start RFIFO eDMA channel but it works fine. Can someone help me on this topic?

Best,

[0xEC · Accepted solution]

I solved the issue.

While using SDK's eqADC driver init API disables eDMA request after transfer complete.

 

I disabled it by calling this function:

After this disable, eDMA works when eqADC requests to fill CFIFO and drain RFIFO.

[davidtosenovjan]

No, you should not trigger any DMA transfer manually. It is supposed to be triggered by eQADC module (by CFFFx and RFDFx flag).

If CFIFOx is not full DMA transfer is triggered by eQADC and loads one command to the CFIFO. If RFIFOx is not empty DMA transfer is triggered by eQADC and drains one result from the RFIFOx.

[0xEC]

But after first fill of Command FIFO and after that result FIFO by eDMA, there is no further filling by eDMA even if these conditions are met