eTPU Coherency Mechanism

[erdinc26]

Hello, I am working on etpu on MPC5674F card.

There are some unclear situations between the interaction between Host-eTPU. I would be glad if you can help me clarify these issues.
I do not use CDC and other things on eTPU and I perform write-read operations directly from the host. But I could not fully understand what the priority would be if eTPU and Host accessed these parameters at the same time.
Is there a possible deadlock here? If so, is there a time limit?

Best regards

[davidtosenovjan]

If CPU and eTPU engine both attempts to access shared RAM, micro engine can suspend its thread execution for two system clocks if CPU is currently accessing the shared RAM. Likewise, the CPU receives two wait states if tries to access shared RAM while micro-engine performing the access. This is called “collision”.

Coherency issues could possibly happen from application point of view, thus in case one parameter is updated and second one not. For this purpose, there is Coherent Dual-parameter Controller (CDC) implemented there:

Pay attention to section 5.7.3 in eTPURM:

https://www.nxp.com/docs/en/reference-manual/ETPURM.pdf