Using MPC5777C M_CAN RAM while keeping M_CAN inactive

[ricardofranca]

Hello,

I intend to use the M_CAN RAM as a standard RAM, shared between cores, so that I can keep each main SRAM bank exclusive to one CPU. Will the M_CAN RAM work normally if I set M_CAN_CCCR[CSR] (to make sure M_CAN itself remains inactive)?

By the way: is it possible to do the same with other peripherals that have their own RAM memories (if I got it right, these are FlexCAN, eDMA, FEC, eTPU and CSE)?

Thanks!

Ricardo

[davidtosenovjan]

There is only little customer demand for this as it is not intended operation not being well described in the documentation. There may be limitation in the meaning data width and misaligned access as these embedded fits for different purposes.

I have been answering  eTPU part in the past:

“It is possible to use eTPU RAM as normal RAM, but access will be slower as it goes over PBRIDGE and with limits.

eTPU Parameter RAM (SDM) can be accesses without limitation.

To have host access to the eTPU Code RAM (SCM) you need to set the VIS bit in the ETPU_MCR. This bit is write protected unless both eTPU engines are halted or stopped. So first you must write a 1 to the STOP bit in each eTPU engines Engine Control Register (ECR).

The STOP bits will be write protected whilst ETPU_MCR.VIS=1. So you can't run ETPU code with SCM accesses and allow the host to access the SCM at the same time.

Only 32-bit aligned access are supported to SCM. 64/16/8-bit accesses are not supported.”

Also I can confirm you can use this way FlexCAN, eDMA, probably also MCAN embedded RAMs.

CSE certainly not as it is all locked and as I know FEC uses pointer to ordinary RAM, so it does not use embedded RAM.