Using MPC5777C Data cache as SRAM

[Kothe1995]

Wanted to use MPC5777C 16kB data cache as SRAM. Need to understand how to configure data cache as SRAM and also at what address space of MPC5777C data cache is available.

[davidtosenovjan]

A procedure you may find in the section 9 (DCache is configured the same way as unified cache on MPC5500

https://www.nxp.com/docs/en/application-note/AN2865.pdf

Possibly I could offer my example code for MPC5676R which device is using the same core, so Dcache configuration (file Optimizations.c) is compatible:

https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-XPC567XRKIT-PinToggleStationery-CW210/ta...

It is needed to create virtual address space according to DCache size out of used ranges for other memories.

Possibly following thread could be useful for you:

https://community.nxp.com/t5/MPC5xxx/Dcache-as-RAM-in-MPC5777C/m-p/1660816/highlight/false#M23737

[Kothe1995]

I wanted to disable data cache and use the data cache memory as SRAM, that means the SRAM space will increase by 16kb of data cache. I also wanted to verify it by using the data cache address in the way we access SRAM. 

[davidtosenovjan]

Yes, it can be done Actually on this device is is common practice to put stack to the locked cache. As this device is not equipped with TCM (i.e. DMEM) memory, cache is the fastest local memory.

For instance in this example code you may see it as part of startup (init.s):
https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5777C-PinToggleStationery-GHS714/ta-p...

[Kothe1995]

init.s is not present in above example code

[davidtosenovjan]

I can see it there.