Synchronization requirements for tlbwe instruction (e200z7)

[ricardofranca]

Hello,

When booting a MPC5777C, I had some trouble understanding the synchronization requirements for the tlbwe instruction. From EREF_RM table 4-3, I (think I) understood that:
  For data access synchronization, we must use a CSI instruction before tlbwe and another after tlbwe. Note 5 shows a case where an extra msync may be necessary after tlbwe.
  For instruction fetch/execution synchronization, only a CSI instruction after tlbwe is necessary. Note 2 shows a case where an extra msync may be necessary after tlbwe.

AN5191 shows an example where no synchronizations are performed, except for the TLB page that is running the MMU configuration itself. In this case, an msync is performed before tlbwe and isync is performed after tlbwe. My questions are:

- When can I be sure no CSI instructions are needed for tlbwe?
- In the AN5191 example, can se_isync be replaced by any other CSI instruction?
- In the AN5191 example, why is the msync inserted before tlbwe? Is this equivalent to the EREF note that describes the possible need for an extra msync after tlbwe? Or there is some other case where an msync would be necessary before tlbwe?
- EREF_RM table 4-41 describes msync as performing instruction and memory synchronization. Why would I need a CSI instruction after msync?

Thanks,

Ricardo

[davidtosenovjan]

Table 5-3. Data Access Synchronization Requirements and Table 5-4. Instruction Fetch and/or Execution Synchronization Requirements explicitly defines synchronization requirements for tlbwe.

Usual sequence is

msync

tlbwe

isync

Q: When can I be sure no CSI instructions are needed for tlbwe?

A: It is better to do it bulletproof and put it there always then later dealing with issues caused by missing synch instructions. Changing context takes several cycles and if new context is not touched during this time (for instance definition of memory that wasn’t defined before), then will be no issue. In case AN5191, it is startup code and tlbwe is followed by another register loading and definition of another TLB, so in this it is OK exludion TLB1 or TLB3.

Q: In the AN5191 example, can se_isync be replaced by any other CSI instruction?

A: Yes, if it does make sense. The notation “CSI” in the tables means any context-synchronizing instruction (sc, isync, rfi, rfgi <E.HV>, rfci, rfdi <E.ED>, or rfmci). In AN5191 it does not make any sense.

Q: In the AN5191 example, why is the msync inserted before tlbwe? Is this equivalent to the EREF note that describes the possible need for an extra msync after tlbwe? Or there is some other case where an msync would be necessary before tlbwe?

A: Not sure which note you have on your mind, but it is possible. I would keep standard sequence as we have for instance in MAS TLB calculator:

https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/MMU-Assist-Register-CONFIGURATOR/ta-p/1110436

Q: EREF_RM table 4-41 describes msync as performing instruction and memory synchronization. Why would I need a CSI instruction after msync?

A: You apparently don’t have document that is up to date. Latest version is EREFRM Rev. 1 12/2007. Isync is required by tlbwe as I already mentioned.

[ricardofranca]

Hello David,

I am using EREF 2.0 Rev. 0 09/2011 - it is the most recent one I have found and I cannot find another version besides this one (https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/mpc5xxx/3777/1/EREFRM.pdf).

The tables I can see are:

I understand it makes sense to finish all transactions before writing TLB entries but I could not find the explicit requirement for the "msync before tlbwe" anywhere in the document. Can you point me the location of this requirement, so that I can refer to it in my own documentation?

The note I mentioned is note 5 of the first table I pasted here: "if these completions must be ensured, tlbwe, tlbilx <E.HV>, or tlbivax must be followed by a sync and by a context-synchronizing instruction". May I ignore this note if I used a msync before tlbwe?

Finally, my colleagues and I are all about using a general synchronization instruction pattern that would fit any case. Thus, if msync-tlbwe-isync covers all cases, we will use it even when we could use less (or lighter) instructions. All we need is some reference to point to when explaining this pattern.

Thanks!

[davidtosenovjan]

Latest version you can download on our web:

However sequence is msync, tlbwe, isync is proven one, widely used.

According EREFrequirements is seems isync could be put before tlbwe (there's nothing wrong with adding it there, so if you use msync, isync, tlbwe, isync).

Apparently is it performance optimized as it is used during startup and there no accesses to memories, only core registers and instruction fetches. It would probably require deeper analysis.

Also there are certain requirement for mtspr (MASn) operation.