Simulation of loss of lock

[yixinwu]

Hello community,

In MPC5744P there are FCCU faults (NCF[24] and NCF[25]) defined for detection of loss of lock. These 2 faults are not injectable. The LOLF bit of PLLDIG_PLL0SR register is w1c. Is there any possibility that the faults can be simulated? Thank you.

For configuration I have done this:

PLLDIG.PLL0CR.B.LOLIE = 1

PLLDIG.PLL1CR.B.LOLIE = 1

[davidtosenovjan · Accepted solution]

Loss-of-lock condition can be generate the way that SW configures FMPLL with IRC as reference, waiting for lock and then it suddenly changes clock source from IRC to XOSC what should cause loss of lock and should not cause loss of clock as clock sources are untouched.

[yixinwu]

Thank you for your reply.

I have tried re-configuration of MC_CGM.AC3_SC.B.SELCTL and MC_CGM.AC4_SC.B.SELCTL, but nothing happened. (no NCF[24] or NCF[25])

I have then tried to modify the FDEN bit of PLLDIG_PLL1FD, but nothing happened either.

[yixinwu]

I am sorry I have used a wrong version of my software. Now the problem is solved. The loss of lock can be monitored by FCCU. Thank you very much for your support.