Self Test Complet Reset

[kpitsupportshas]

Hi,

While getting the reset reason from Freescale MCAL function Mcu_GetResetReason() for MPC 5748G , the reset reason is returned as Self test completed irrespective of reset created (Power on, sw destructive reset etc). It is also noted that F_ST_DONE bit is set  always set in MC_RGM_FES register after any reset (Power on, sw destructive reset etc).

Note : SUF_DIS bit in UTEST miscellaneous register set as 1.

Please let us know why reset reason is always set to self test completed.

Regards,

Nijeesh

[kpitsupportshas]

Hi,

Thanks for the reply.

Please let us know how we can disable the BIST.

Regards,

Nijeesh

[petervlna]

This is described in Reference Manual:

77.8.3 Bypass USER Mode
In this case, the USER application parameters stored in FLASH and read by SSCM are written in order to skip the Self-Test procedure after a reset trigger event is applied. It might be useful in case the device is not configured for applications requiring improved reliability. The sequence is the following:
1. Unlock the STCU2 access writing the Off-Line Key1/Key2 sequence into the STCU2_SKC register
2. Set the BYP bit in the STCU2_RUN register After BYP bit is set, the core clock is switched off, the Self-Test sequence is not applied and the system can wake up and start the user application.

Remember that you must use DCF records to set BYP during reset.

For details about DCF see reference manual:

Chapter 11: Device Configuration Format (DCF) records

Peter

[petervlna]

Hi,

If the BIST (build in self test) is enabled (by default) then during reset phase 3 the BIST is executed. After BIST the device is reset by BIST itself to reset phase1. Then it validates BIST complete bit during reset phase3 and skip the BIST if the BIST was already executed. Then device start execution from DRUN mode.

The BIST is not executed only on short functional reset event or when BIST is disabled.

You will always see the F_ST_DONE bit set if BIST is enabled and reset was triggered (except short functional reset) as last valid reset source.

Along with F_ST_DONE there should be more flags set in RGM (FES/DES) registers. Check it with debugger after reset to find if there was any other reset source.

Peter