HI Petr
Follow your advice ，The following code has been added。
EDMA.TCD[DMA_CHANNEL].SLAST.R = -16; /* address Adjustment after major loops */
EDMA.TCD[DMA_CHANNEL].DLASTSGA.R = -16; /* addr adjustment after major loop */
EDMA.TCD[DMA_CHANNEL].CSR.B.DREQ = 0; /* do not Disable Request */
When i send data for the first time ID: 0X555 data:FF 02 03 04 05 06 07 08 The data in the FIFO buffer is as follows。
The data in the RxDATA[] buffer is as follows。
When i send data for the second time ID: 0X555 data:EE 02 03 04 05 06 07 08 The data in the FIFO buffer is as follows。
The data in the RxDATA[] buffer is as follows。
Summary: Both DMA interrupts can be entered normally，The first time the data received by the FIFO is normal, the data carried by the DMA is also normal。The data received in the second FIFO is significantly different from the data sent，The DMA entry interrupt seems to indicate that the DMA has carried out the handling operation normally，But the data in RxDATA[] seems to be the first data sent，When the second DMA interrupt is completed, there is a problem with the data received by the CAN FIFO And DMA did not carry the wrong data received。
