S32R274 updates a specific variable in the data cache

[dong06]

Hello, I have some chip S32R274 data cache issues.

The first is to enable the cache function. Is it possible to enable the data caching function of the relevant kernel by setting DCINV directly after setting DCE of L1CSR0?

The second issue is whether the specified variables can be set to use caching instead of all variables being cached once enabled?

In addition, the description of cache function in the reference manual is not clear enough. I need more information about the data cache of this chip. Could you share it?

Looking forward to your reply!

[lukaszadrapa]

Hi,

The procedure to enable cache memory can be found in AN12553, section 7.5.6 Enable cache:

https://www.nxp.com/docs/en/application-note/AN12553.pdf

And also in startup files of a project created by S32 Design Studio IDE:

You can use SMPU module to define which areas will be cacheable and which will be cache inhibited. There’s CI bit in SMPU_RGDn_WORD3 register.

If you use SDK, it can be configured here:

An example of SMPU configuration without SDK can be found here (for different MCU):

https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5748G-SMPU-initialization-Process-ID-...

Regards,

Lukas

[dong06]

Let me try.

Thank you for your answer, Lukas!