Receiving junk data while communicating with External peripherals at 33 Mhz with DSPI_C in MPC5674F

[CNarendra]

Hello,

I have interfaced the MPC5674F DSPI_C channel with a NOR Flash (S25FL512S). The communication works correctly at 16 MHz, and I am able to read the status register, returning 0x82 as expected. However, when I increase the clock speed to 33 MHz, the data read by the software is incorrect (0xC1 instead of 0x82).

Observations:

1. I probed the MISO and CLK signals using an oscilloscope.
2. At both 16 MHz and 33 MHz, the oscilloscope shows the correct data (0x82) being transmitted from the flash.
3. Despite this, the data read by the software is manipulated and incorrect at 33 MHz.

I am attaching screenshots of the waveforms for both clock speeds:

                           Waveform @ 16MHz

CNarendra_0-1737181962851.jpeg

                            Waveform @33 MHz

CNarendra_1-1737182021830.jpeg

software_read@33 MHz

CNarendra_2-1737182564564.png

software_read@16 MHz

CNarendra_3-1737182637192.png

CNarendra_4-1737182902482.png

CNarendra_5-1737182957426.png

CNarendra_6-1737183039410.png

Could you help me identify the root cause of this issue? Specifically, why is the software misinterpreting the correct data at 33 MHz, even though the waveforms appear correct on the oscilloscope? Could this be related to timing, configuration, or any limitations of the DSPI interface at higher clock speeds?

Looking forward to your insights.

Thank you!
Narendra .C

# MPC5674F, #SPI 

[PetrS · Accepted solution]

Hi,

try to use Modified Transfer Format (MTFE=1) and delay sampling of SIN by setting SMPL_PT bits. See more in chapter 24.4.7.3 Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 0) of the device RM.

BR, Petr

[CNarendra]

Hi @PetrS,

The issue is resolved, and the communication is working fine at 33 MHz after configuring MTFE = 1 and SMPL_PT = 1 as suggested. Thank you for your guidance!

I have a follow-up question:

In the Modified Transfer Format, the master samples data on odd clock cycles. Could this behavior impact the overall performance or data throughput of the system in any way?

Looking forward to your insights.

Best regards,
Narendra

MPC5674F ,#DSPI

[PetrS]

Hi,

CPHA specifies sampling edge (odd or even), not MTFE. In MTFE you can delay SIN sampling from selected SCK edge by amount of 1 or 2 system clocks, as shown e.g in Figure 24-31. DSPI Modified Transfer Format (MTFE=1, CPHA=0, fsck = fperiph/4)
This not not affect overall performance or data throughput.

BR, Petr